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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for the device.  <a href="struct_x_scu_gic___config.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_scu_gic.html">XScuGic</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> driver instance data.  <a href="struct_x_scu_gic.html#details">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga0756f011ef667460d583017366823244"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga0756f011ef667460d583017366823244">DEFAULT_PRIORITY</a>&#160;&#160;&#160;0xa0a0a0a0U</td></tr>
<tr class="memdesc:ga0756f011ef667460d583017366823244"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default value for priority_level register.  <a href="#ga0756f011ef667460d583017366823244">More...</a><br/></td></tr>
<tr class="separator:ga0756f011ef667460d583017366823244"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f2c28f54da589ba1000235cfb0929ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga9f2c28f54da589ba1000235cfb0929ba">XSCUGIC_H</a></td></tr>
<tr class="memdesc:ga9f2c28f54da589ba1000235cfb0929ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; prevent circular inclusions  <a href="#ga9f2c28f54da589ba1000235cfb0929ba">More...</a><br/></td></tr>
<tr class="separator:ga9f2c28f54da589ba1000235cfb0929ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0756f011ef667460d583017366823244"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga0756f011ef667460d583017366823244">DEFAULT_PRIORITY</a>&#160;&#160;&#160;0xa0a0a0a0U</td></tr>
<tr class="memdesc:ga0756f011ef667460d583017366823244"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default value for priority_level register.  <a href="#ga0756f011ef667460d583017366823244">More...</a><br/></td></tr>
<tr class="separator:ga0756f011ef667460d583017366823244"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac1bc762eba383937d08c41704737091c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gac1bc762eba383937d08c41704737091c">XSCUGIC_HW_H</a></td></tr>
<tr class="memdesc:gac1bc762eba383937d08c41704737091c"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; prevent circular inclusions  <a href="#gac1bc762eba383937d08c41704737091c">More...</a><br/></td></tr>
<tr class="separator:gac1bc762eba383937d08c41704737091c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1027fc01e0c0efc80eadd0e6bb69f801"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga1027fc01e0c0efc80eadd0e6bb69f801">XSCUGIC_MAX_NUM_INTR_INPUTS</a>&#160;&#160;&#160;195U</td></tr>
<tr class="memdesc:ga1027fc01e0c0efc80eadd0e6bb69f801"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of interrupt defined by Zynq Ultrascale Mp.  <a href="#ga1027fc01e0c0efc80eadd0e6bb69f801">More...</a><br/></td></tr>
<tr class="separator:ga1027fc01e0c0efc80eadd0e6bb69f801"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1706d457c89d8e76f1d120cc6fad418b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>&#160;&#160;&#160;0x20U</td></tr>
<tr class="memdesc:ga1706d457c89d8e76f1d120cc6fad418b"><td class="mdescLeft">&#160;</td><td class="mdescRight">First Interrupt Id for SPI interrupts.  <a href="#ga1706d457c89d8e76f1d120cc6fad418b">More...</a><br/></td></tr>
<tr class="separator:ga1706d457c89d8e76f1d120cc6fad418b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaecd562b440bde835a8eee0c8a0e78249"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaecd562b440bde835a8eee0c8a0e78249">XSCUGIC_MAX_INTR_PRIO_VAL</a>&#160;&#160;&#160;248U</td></tr>
<tr class="memdesc:gaecd562b440bde835a8eee0c8a0e78249"><td class="mdescLeft">&#160;</td><td class="mdescRight">The maximum priority value that can be used in the GIC.  <a href="#gaecd562b440bde835a8eee0c8a0e78249">More...</a><br/></td></tr>
<tr class="separator:gaecd562b440bde835a8eee0c8a0e78249"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga314e70261cb0c4c4da8019ff78c7e6f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga314e70261cb0c4c4da8019ff78c7e6f8">XSCUGIC_INTR_PRIO_MASK</a>&#160;&#160;&#160;0x000000F8U</td></tr>
<tr class="memdesc:ga314e70261cb0c4c4da8019ff78c7e6f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Interrupt priority mask value.  <a href="#ga314e70261cb0c4c4da8019ff78c7e6f8">More...</a><br/></td></tr>
<tr class="separator:ga314e70261cb0c4c4da8019ff78c7e6f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1aea23f3bd1941b93443e441bd1e8e58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga1aea23f3bd1941b93443e441bd1e8e58">XSCUGIC_PEND_INTID_MASK</a>&#160;&#160;&#160;0x000003FFU</td></tr>
<tr class="memdesc:ga1aea23f3bd1941b93443e441bd1e8e58"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pending Interrupt ID.  <a href="#ga1aea23f3bd1941b93443e441bd1e8e58">More...</a><br/></td></tr>
<tr class="separator:ga1aea23f3bd1941b93443e441bd1e8e58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb56c44f88d7770aadf2b1fdbd3c24da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaeb56c44f88d7770aadf2b1fdbd3c24da">XSCUGIC_PCELL_ID</a>&#160;&#160;&#160;0xB105F00DU</td></tr>
<tr class="memdesc:gaeb56c44f88d7770aadf2b1fdbd3c24da"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCELL ID value.  <a href="#gaeb56c44f88d7770aadf2b1fdbd3c24da">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga2cbf5d5ac5273e00c0b16bd33ad0707f"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga2cbf5d5ac5273e00c0b16bd33ad0707f">XScuGic_DeviceInitialize</a> (u32 DeviceId)</td></tr>
<tr class="memdesc:ga2cbf5d5ac5273e00c0b16bd33ad0707f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes the GIC based on the device ID.  <a href="#ga2cbf5d5ac5273e00c0b16bd33ad0707f">More...</a><br/></td></tr>
<tr class="separator:ga2cbf5d5ac5273e00c0b16bd33ad0707f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96bfe161e3b4e401f76f2b35df9fab86"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler</a> (void *DeviceId)</td></tr>
<tr class="memdesc:ga96bfe161e3b4e401f76f2b35df9fab86"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the primary interrupt handler for the driver.  <a href="#ga96bfe161e3b4e401f76f2b35df9fab86">More...</a><br/></td></tr>
<tr class="separator:ga96bfe161e3b4e401f76f2b35df9fab86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac1d1444968ff82f78505eeae32a2e471"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gac1d1444968ff82f78505eeae32a2e471">XScuGic_RegisterHandler</a> (UINTPTR BaseAddress, s32 InterruptID, Xil_InterruptHandler IntrHandler, void *CallBackRef)</td></tr>
<tr class="memdesc:gac1d1444968ff82f78505eeae32a2e471"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register a handler function for a specific interrupt ID.  <a href="#gac1d1444968ff82f78505eeae32a2e471">More...</a><br/></td></tr>
<tr class="separator:gac1d1444968ff82f78505eeae32a2e471"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8e95bba26e2b07a882cb03750540b4d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gac8e95bba26e2b07a882cb03750540b4d">XScuGic_SetPriTrigTypeByDistAddr</a> (UINTPTR DistBaseAddress, u32 Int_Id, u8 Priority, u8 Trigger)</td></tr>
<tr class="memdesc:gac8e95bba26e2b07a882cb03750540b4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the interrupt priority and trigger type for the specificd IRQ source.  <a href="#gac8e95bba26e2b07a882cb03750540b4d">More...</a><br/></td></tr>
<tr class="separator:gac8e95bba26e2b07a882cb03750540b4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga19437ca93adc808161232c5667d7ca62"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga19437ca93adc808161232c5667d7ca62">XScuGic_GetPriTrigTypeByDistAddr</a> (UINTPTR DistBaseAddress, u32 Int_Id, u8 *Priority, u8 *Trigger)</td></tr>
<tr class="memdesc:ga19437ca93adc808161232c5667d7ca62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets the interrupt priority and trigger type for the specificd IRQ source.  <a href="#ga19437ca93adc808161232c5667d7ca62">More...</a><br/></td></tr>
<tr class="separator:ga19437ca93adc808161232c5667d7ca62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaadf6b084a0540093dd64b8a8e3e74d6c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaadf6b084a0540093dd64b8a8e3e74d6c">XScuGic_InterruptMapFromCpuByDistAddr</a> (UINTPTR DistBaseAddress, u8 Cpu_Id, u32 Int_Id)</td></tr>
<tr class="memdesc:gaadf6b084a0540093dd64b8a8e3e74d6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the target CPU for the interrupt of a peripheral.  <a href="#gaadf6b084a0540093dd64b8a8e3e74d6c">More...</a><br/></td></tr>
<tr class="separator:gaadf6b084a0540093dd64b8a8e3e74d6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga51ba67d5953cb6b68a8d327b5e3103d7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga51ba67d5953cb6b68a8d327b5e3103d7">XScuGic_InterruptUnmapFromCpuByDistAddr</a> (UINTPTR DistBaseAddress, u8 Cpu_Id, u32 Int_Id)</td></tr>
<tr class="memdesc:ga51ba67d5953cb6b68a8d327b5e3103d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unmaps specific SPI interrupt from the target CPU.  <a href="#ga51ba67d5953cb6b68a8d327b5e3103d7">More...</a><br/></td></tr>
<tr class="separator:ga51ba67d5953cb6b68a8d327b5e3103d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7192c00a59e0cca27ed4c46f2755bb0"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gac7192c00a59e0cca27ed4c46f2755bb0">XScuGic_UnmapAllInterruptsFromCpuByDistAddr</a> (UINTPTR DistBaseAddress, u8 Cpu_Id)</td></tr>
<tr class="memdesc:gac7192c00a59e0cca27ed4c46f2755bb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unmaps all SPI interrupts from the target CPU.  <a href="#gac7192c00a59e0cca27ed4c46f2755bb0">More...</a><br/></td></tr>
<tr class="separator:gac7192c00a59e0cca27ed4c46f2755bb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadaa95193630e661a6a578f35a5e3ea1a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gadaa95193630e661a6a578f35a5e3ea1a">XScuGic_EnableIntr</a> (UINTPTR DistBaseAddress, u32 Int_Id)</td></tr>
<tr class="memdesc:gadaa95193630e661a6a578f35a5e3ea1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the interrupt source provided as the argument Int_Id.  <a href="#gadaa95193630e661a6a578f35a5e3ea1a">More...</a><br/></td></tr>
<tr class="separator:gadaa95193630e661a6a578f35a5e3ea1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d183d23d05aac5d61cd640c5b39b275"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga0d183d23d05aac5d61cd640c5b39b275">XScuGic_DisableIntr</a> (UINTPTR DistBaseAddress, u32 Int_Id)</td></tr>
<tr class="memdesc:ga0d183d23d05aac5d61cd640c5b39b275"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables the interrupt source provided as the argument Int_Id so that the interrupt controller will not cause interrupts for the specified Int_Id.  <a href="#ga0d183d23d05aac5d61cd640c5b39b275">More...</a><br/></td></tr>
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Variables</h2></td></tr>
<tr class="memitem:ga5f67ecf54244b46e2570691626906397"><td class="memItemLeft" align="right" valign="top">Xil_InterruptHandler&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga5f67ecf54244b46e2570691626906397">XScuGic_VectorTableEntry::Handler</a></td></tr>
<tr class="memdesc:ga5f67ecf54244b46e2570691626906397"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Handler.  <a href="#ga5f67ecf54244b46e2570691626906397">More...</a><br/></td></tr>
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<tr class="memitem:ga6969d00688039e7e14b25fadd8227398"><td class="memItemLeft" align="right" valign="top">void *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga6969d00688039e7e14b25fadd8227398">XScuGic_VectorTableEntry::CallBackRef</a></td></tr>
<tr class="memdesc:ga6969d00688039e7e14b25fadd8227398"><td class="mdescLeft">&#160;</td><td class="mdescRight">CallBackRef is the callback reference passed in by the upper layer when setting the Interrupt handler for specific interrupt ID, and it will passed back to Interrupt handler when it is invoked.  <a href="#ga6969d00688039e7e14b25fadd8227398">More...</a><br/></td></tr>
<tr class="separator:ga6969d00688039e7e14b25fadd8227398"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga243bdaa82f8b278f13ecb124b9cc7cd3"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga243bdaa82f8b278f13ecb124b9cc7cd3">XScuGic_Config::DeviceId</a></td></tr>
<tr class="memdesc:ga243bdaa82f8b278f13ecb124b9cc7cd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unique ID of device.  <a href="#ga243bdaa82f8b278f13ecb124b9cc7cd3">More...</a><br/></td></tr>
<tr class="separator:ga243bdaa82f8b278f13ecb124b9cc7cd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1bb3866706357e2cd84c657e0e703986"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga1bb3866706357e2cd84c657e0e703986">XScuGic_Config::CpuBaseAddress</a></td></tr>
<tr class="memdesc:ga1bb3866706357e2cd84c657e0e703986"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU Interface Register base address.  <a href="#ga1bb3866706357e2cd84c657e0e703986">More...</a><br/></td></tr>
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<tr class="memitem:ga699bf6b8bb8bfbb652b647b78cfae695"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga699bf6b8bb8bfbb652b647b78cfae695">XScuGic_Config::DistBaseAddress</a></td></tr>
<tr class="memdesc:ga699bf6b8bb8bfbb652b647b78cfae695"><td class="mdescLeft">&#160;</td><td class="mdescRight">Distributor Register base address.  <a href="#ga699bf6b8bb8bfbb652b647b78cfae695">More...</a><br/></td></tr>
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<tr class="memitem:ga7ea39fc648dff09faa2a238e9a054089"><td class="memItemLeft" align="right" valign="top">XScuGic_VectorTableEntry&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a> [<a class="el" href="group__scugic__api.html#ga1027fc01e0c0efc80eadd0e6bb69f801">XSCUGIC_MAX_NUM_INTR_INPUTS</a>]</td></tr>
<tr class="memdesc:ga7ea39fc648dff09faa2a238e9a054089"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vector table of interrupt handlers.  <a href="#ga7ea39fc648dff09faa2a238e9a054089">More...</a><br/></td></tr>
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<tr class="memitem:ga231f58b4755a1856bbe3120370e5889e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga231f58b4755a1856bbe3120370e5889e">XScuGic::Config</a></td></tr>
<tr class="memdesc:ga231f58b4755a1856bbe3120370e5889e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configuration table entry.  <a href="#ga231f58b4755a1856bbe3120370e5889e">More...</a><br/></td></tr>
<tr class="separator:ga231f58b4755a1856bbe3120370e5889e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga797e50fb56fbc19bc35f73896decaf82"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a></td></tr>
<tr class="memdesc:ga797e50fb56fbc19bc35f73896decaf82"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device is initialized and ready.  <a href="#ga797e50fb56fbc19bc35f73896decaf82">More...</a><br/></td></tr>
<tr class="separator:ga797e50fb56fbc19bc35f73896decaf82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fa65e4df0e0d8da24a557e1398c9df8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga1fa65e4df0e0d8da24a557e1398c9df8">XScuGic::UnhandledInterrupts</a></td></tr>
<tr class="memdesc:ga1fa65e4df0e0d8da24a557e1398c9df8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intc Statistics.  <a href="#ga1fa65e4df0e0d8da24a557e1398c9df8">More...</a><br/></td></tr>
<tr class="separator:ga1fa65e4df0e0d8da24a557e1398c9df8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca56d0e0512f7fb4430977d6b6d598a9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaca56d0e0512f7fb4430977d6b6d598a9">XScuGic_ConfigTable</a> [XPAR_XSCUGIC_NUM_INSTANCES]</td></tr>
<tr class="memdesc:gaca56d0e0512f7fb4430977d6b6d598a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This table contains configuration information for each GIC device in the system.  <a href="#gaca56d0e0512f7fb4430977d6b6d598a9">More...</a><br/></td></tr>
<tr class="separator:gaca56d0e0512f7fb4430977d6b6d598a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
EFUSE status Register information</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp9eb45bd8aa188ce25c6e90e4aad39114"></a>EFUSE Status Register </p>
</td></tr>
<tr class="memitem:ga07d27bd67c789603a7130283855f0c53"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga07d27bd67c789603a7130283855f0c53"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>EFUSE_STATUS_OFFSET</b>&#160;&#160;&#160;0x10</td></tr>
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<tr class="memitem:gabf7f61958eba005dd02a7014a664def5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabf7f61958eba005dd02a7014a664def5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>EFUSE_STATUS_CPU_MASK</b>&#160;&#160;&#160;0x80</td></tr>
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<tr class="memitem:ga3dde6ae31d569b01dc88903a5340d744"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga3dde6ae31d569b01dc88903a5340d744">ARMA9</a></td></tr>
<tr class="memdesc:ga3dde6ae31d569b01dc88903a5340d744"><td class="mdescLeft">&#160;</td><td class="mdescRight">ARMA9 macro to identify cortexA9.  <a href="#ga3dde6ae31d569b01dc88903a5340d744">More...</a><br/></td></tr>
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GICD_CTLR Register information</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp2b456a55406635bf4ed57e8208932672"></a>GICD_CTLR Status Register </p>
</td></tr>
<tr class="memitem:ga3de9d984ad4026ce214e09bf796cdc49"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga3de9d984ad4026ce214e09bf796cdc49">XScuGic_ConfigTable</a> []</td></tr>
<tr class="memdesc:ga3de9d984ad4026ce214e09bf796cdc49"><td class="mdescLeft">&#160;</td><td class="mdescRight">Config table.  <a href="#ga3de9d984ad4026ce214e09bf796cdc49">More...</a><br/></td></tr>
<tr class="separator:ga3de9d984ad4026ce214e09bf796cdc49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8e0bfe31c0fa2ca654c36715a3c13f8"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">XScuGic_CfgInitialize</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, <a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *ConfigPtr, u32 EffectiveAddr)</td></tr>
<tr class="memdesc:gaf8e0bfe31c0fa2ca654c36715a3c13f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">CfgInitialize a specific interrupt controller instance/driver.  <a href="#gaf8e0bfe31c0fa2ca654c36715a3c13f8">More...</a><br/></td></tr>
<tr class="separator:gaf8e0bfe31c0fa2ca654c36715a3c13f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga48f9dd531aa861a74e6bd627943573ea"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga48f9dd531aa861a74e6bd627943573ea">XScuGic_Connect</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, Xil_InterruptHandler Handler, void *CallBackRef)</td></tr>
<tr class="memdesc:ga48f9dd531aa861a74e6bd627943573ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Makes the connection between the Int_Id of the interrupt source and the associated handler that is to run when the interrupt is recognized.  <a href="#ga48f9dd531aa861a74e6bd627943573ea">More...</a><br/></td></tr>
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<tr class="memitem:gad162acedbbd41fd890fc7f2225ed480b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gad162acedbbd41fd890fc7f2225ed480b">XScuGic_Disconnect</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
<tr class="memdesc:gad162acedbbd41fd890fc7f2225ed480b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Updates the interrupt table with the Null Handler and NULL arguments at the location pointed at by the Int_Id.  <a href="#gad162acedbbd41fd890fc7f2225ed480b">More...</a><br/></td></tr>
<tr class="separator:gad162acedbbd41fd890fc7f2225ed480b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac965b9e3ae7668a92cf07a65bde142cc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gac965b9e3ae7668a92cf07a65bde142cc">XScuGic_Enable</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
<tr class="memdesc:gac965b9e3ae7668a92cf07a65bde142cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the interrupt source provided as the argument Int_Id.  <a href="#gac965b9e3ae7668a92cf07a65bde142cc">More...</a><br/></td></tr>
<tr class="separator:gac965b9e3ae7668a92cf07a65bde142cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaafd153e16238a1189c513846675e096a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaafd153e16238a1189c513846675e096a">XScuGic_Disable</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id)</td></tr>
<tr class="memdesc:gaafd153e16238a1189c513846675e096a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables the interrupt source provided as the argument Int_Id such that the interrupt controller will not cause interrupts for the specified Int_Id.  <a href="#gaafd153e16238a1189c513846675e096a">More...</a><br/></td></tr>
<tr class="separator:gaafd153e16238a1189c513846675e096a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca28a576540ab5fcd75cee1f38917ae4"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaca28a576540ab5fcd75cee1f38917ae4">XScuGic_SoftwareIntr</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u32 Cpu_Identifier)</td></tr>
<tr class="memdesc:gaca28a576540ab5fcd75cee1f38917ae4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Allows software to simulate an interrupt in the interrupt controller.  <a href="#gaca28a576540ab5fcd75cee1f38917ae4">More...</a><br/></td></tr>
<tr class="separator:gaca28a576540ab5fcd75cee1f38917ae4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79abd6248cb578142e9c475f20dbeb06"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u8 Priority, u8 Trigger)</td></tr>
<tr class="memdesc:ga79abd6248cb578142e9c475f20dbeb06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the interrupt priority and trigger type for the specificd IRQ source.  <a href="#ga79abd6248cb578142e9c475f20dbeb06">More...</a><br/></td></tr>
<tr class="separator:ga79abd6248cb578142e9c475f20dbeb06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ed162180ffb45b082c2fbe23951ba13"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u32 Int_Id, u8 *Priority, u8 *Trigger)</td></tr>
<tr class="memdesc:ga6ed162180ffb45b082c2fbe23951ba13"><td class="mdescLeft">&#160;</td><td class="mdescRight">Gets the interrupt priority and trigger type for the specificd IRQ source.  <a href="#ga6ed162180ffb45b082c2fbe23951ba13">More...</a><br/></td></tr>
<tr class="separator:ga6ed162180ffb45b082c2fbe23951ba13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2a94f1a519d965f051d598e5a6b5a855"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga2a94f1a519d965f051d598e5a6b5a855">XScuGic_InterruptMaptoCpu</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u8 Cpu_Identifier, u32 Int_Id)</td></tr>
<tr class="memdesc:ga2a94f1a519d965f051d598e5a6b5a855"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the target CPU for the interrupt of a peripheral.  <a href="#ga2a94f1a519d965f051d598e5a6b5a855">More...</a><br/></td></tr>
<tr class="separator:ga2a94f1a519d965f051d598e5a6b5a855"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga04f8ea74458251784b293e4ad98f2d74"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga04f8ea74458251784b293e4ad98f2d74">XScuGic_InterruptUnmapFromCpu</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u8 Cpu_Identifier, u32 Int_Id)</td></tr>
<tr class="memdesc:ga04f8ea74458251784b293e4ad98f2d74"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unmaps specific SPI interrupt from the target CPU.  <a href="#ga04f8ea74458251784b293e4ad98f2d74">More...</a><br/></td></tr>
<tr class="separator:ga04f8ea74458251784b293e4ad98f2d74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga66b2416be64a5e582e530ed9ed7f962c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga66b2416be64a5e582e530ed9ed7f962c">XScuGic_UnmapAllInterruptsFromCpu</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr, u8 Cpu_Identifier)</td></tr>
<tr class="memdesc:ga66b2416be64a5e582e530ed9ed7f962c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unmaps all SPI interrupts from the target CPU.  <a href="#ga66b2416be64a5e582e530ed9ed7f962c">More...</a><br/></td></tr>
<tr class="separator:ga66b2416be64a5e582e530ed9ed7f962c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6146a0489a1c748ceeaee729639d48a7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga6146a0489a1c748ceeaee729639d48a7">XScuGic_Stop</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga6146a0489a1c748ceeaee729639d48a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Checks if the interrupt target register contains all interrupts to be targeted for current CPU.  <a href="#ga6146a0489a1c748ceeaee729639d48a7">More...</a><br/></td></tr>
<tr class="separator:ga6146a0489a1c748ceeaee729639d48a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga945e029b4356be809020c81745c4a23b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga945e029b4356be809020c81745c4a23b">XScuGic_SetCpuID</a> (u32 CpuCoreId)</td></tr>
<tr class="memdesc:ga945e029b4356be809020c81745c4a23b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Updates the CpuId global variable.  <a href="#ga945e029b4356be809020c81745c4a23b">More...</a><br/></td></tr>
<tr class="separator:ga945e029b4356be809020c81745c4a23b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6c30ba79ea9505dc29b9cac4deea3df8"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga6c30ba79ea9505dc29b9cac4deea3df8">XScuGic_GetCpuID</a> (void)</td></tr>
<tr class="memdesc:ga6c30ba79ea9505dc29b9cac4deea3df8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns the CpuId variable.  <a href="#ga6c30ba79ea9505dc29b9cac4deea3df8">More...</a><br/></td></tr>
<tr class="separator:ga6c30ba79ea9505dc29b9cac4deea3df8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72b9aec992716861e5f0929e4d0d9f7c"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga72b9aec992716861e5f0929e4d0d9f7c">XScuGic_IsInitialized</a> (u32 DeviceId)</td></tr>
<tr class="memdesc:ga72b9aec992716861e5f0929e4d0d9f7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Checks whether the XScGic is initialized or not given the device ID.  <a href="#ga72b9aec992716861e5f0929e4d0d9f7c">More...</a><br/></td></tr>
<tr class="separator:ga72b9aec992716861e5f0929e4d0d9f7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab2c0554b809121cc91a96fcd8c749c25"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gab2c0554b809121cc91a96fcd8c749c25">XScuGic_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:gab2c0554b809121cc91a96fcd8c749c25"><td class="mdescLeft">&#160;</td><td class="mdescRight">Looks up the device configuration based on the unique device ID.  <a href="#gab2c0554b809121cc91a96fcd8c749c25">More...</a><br/></td></tr>
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<tr class="memitem:ga805a47295123177a48b07fccfe037702"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga805a47295123177a48b07fccfe037702">XScuGic_LookupConfigBaseAddr</a> (UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:ga805a47295123177a48b07fccfe037702"><td class="mdescLeft">&#160;</td><td class="mdescRight">Looks up the device configuration based on the BaseAddress.  <a href="#ga805a47295123177a48b07fccfe037702">More...</a><br/></td></tr>
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<tr class="memitem:gaa26a952ecd376be0bc3d8433023d1364"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr)</td></tr>
<tr class="memdesc:gaa26a952ecd376be0bc3d8433023d1364"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the primary interrupt handler for the driver.  <a href="#gaa26a952ecd376be0bc3d8433023d1364">More...</a><br/></td></tr>
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<tr class="memitem:ga081a9a62546b413d94e609894282a575"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga081a9a62546b413d94e609894282a575">XScuGic_SelfTest</a> (<a class="el" href="struct_x_scu_gic.html">XScuGic</a> *InstancePtr)</td></tr>
<tr class="memdesc:ga081a9a62546b413d94e609894282a575"><td class="mdescLeft">&#160;</td><td class="mdescRight">Runs a self-test on the driver/device.  <a href="#ga081a9a62546b413d94e609894282a575">More...</a><br/></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSCUGIC500_DCTLR_ARE_NS_ENABLE</b>&#160;&#160;&#160;0x20</td></tr>
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<tr class="memitem:ga28dd6678d0630c07191a41b8f5af0950"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga28dd6678d0630c07191a41b8f5af0950"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSCUGIC500_DCTLR_ARE_S_ENABLE</b>&#160;&#160;&#160;0x10</td></tr>
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<tr class="memitem:ga2a4ba236ff7bfeab20b5ca81082f2b13"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga2a4ba236ff7bfeab20b5ca81082f2b13">XScuGic_CPUWriteReg</a>(InstancePtr, RegOffset, Data)</td></tr>
<tr class="memdesc:ga2a4ba236ff7bfeab20b5ca81082f2b13"><td class="mdescLeft">&#160;</td><td class="mdescRight">Writes the given CPU Interface register.  <a href="#ga2a4ba236ff7bfeab20b5ca81082f2b13">More...</a><br/></td></tr>
<tr class="separator:ga2a4ba236ff7bfeab20b5ca81082f2b13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f3bba7c5247812158ef4fde7a0e7dfe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga2f3bba7c5247812158ef4fde7a0e7dfe">XScuGic_CPUReadReg</a>(InstancePtr, RegOffset)&#160;&#160;&#160;(<a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>(((InstancePtr)-&gt;Config-&gt;CpuBaseAddress), (RegOffset)))</td></tr>
<tr class="memdesc:ga2f3bba7c5247812158ef4fde7a0e7dfe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads the given CPU Interface register.  <a href="#ga2f3bba7c5247812158ef4fde7a0e7dfe">More...</a><br/></td></tr>
<tr class="separator:ga2f3bba7c5247812158ef4fde7a0e7dfe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22e9f81ed00f7cc39df1c6e76988fdb1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>(InstancePtr, RegOffset, Data)</td></tr>
<tr class="memdesc:ga22e9f81ed00f7cc39df1c6e76988fdb1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Writes the given Distributor Interface register.  <a href="#ga22e9f81ed00f7cc39df1c6e76988fdb1">More...</a><br/></td></tr>
<tr class="separator:ga22e9f81ed00f7cc39df1c6e76988fdb1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d639fe1851f9d833367fb4322390eeb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>(InstancePtr, RegOffset)&#160;&#160;&#160;(<a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>(((InstancePtr)-&gt;Config-&gt;DistBaseAddress), (RegOffset)))</td></tr>
<tr class="memdesc:ga3d639fe1851f9d833367fb4322390eeb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads the given Distributor Interface register.  <a href="#ga3d639fe1851f9d833367fb4322390eeb">More...</a><br/></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Distributor Interface Register Map</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp3fe18394515073409dbf777aaf4c11b3"></a>Define the offsets from the base address for all Distributor registers of the interrupt controller, some registers may be reserved in the hardware device. </p>
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<tr class="memitem:ga94cd5e2c3a1ab5b6c282d76bead5d616"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga94cd5e2c3a1ab5b6c282d76bead5d616">XSCUGIC_DIST_EN_OFFSET</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga94cd5e2c3a1ab5b6c282d76bead5d616"><td class="mdescLeft">&#160;</td><td class="mdescRight">Distributor Enable Register.  <a href="#ga94cd5e2c3a1ab5b6c282d76bead5d616">More...</a><br/></td></tr>
<tr class="separator:ga94cd5e2c3a1ab5b6c282d76bead5d616"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga80f182c20ecfcc115bca1ac7aae08889"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga80f182c20ecfcc115bca1ac7aae08889">XSCUGIC_IC_TYPE_OFFSET</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga80f182c20ecfcc115bca1ac7aae08889"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Controller Type Register.  <a href="#ga80f182c20ecfcc115bca1ac7aae08889">More...</a><br/></td></tr>
<tr class="separator:ga80f182c20ecfcc115bca1ac7aae08889"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaff73afc08cc167202d5aac6661ae6a1e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaff73afc08cc167202d5aac6661ae6a1e">XSCUGIC_DIST_IDENT_OFFSET</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gaff73afc08cc167202d5aac6661ae6a1e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Implementor ID Register.  <a href="#gaff73afc08cc167202d5aac6661ae6a1e">More...</a><br/></td></tr>
<tr class="separator:gaff73afc08cc167202d5aac6661ae6a1e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8413fc164b51c233c05c6e48fdc0bf5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaf8413fc164b51c233c05c6e48fdc0bf5">XSCUGIC_SECURITY_OFFSET</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:gaf8413fc164b51c233c05c6e48fdc0bf5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Security Register.  <a href="#gaf8413fc164b51c233c05c6e48fdc0bf5">More...</a><br/></td></tr>
<tr class="separator:gaf8413fc164b51c233c05c6e48fdc0bf5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e39be0cb9e08f4c9231f76e685a76cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga7e39be0cb9e08f4c9231f76e685a76cc">XSCUGIC_ENABLE_SET_OFFSET</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:ga7e39be0cb9e08f4c9231f76e685a76cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Set Register.  <a href="#ga7e39be0cb9e08f4c9231f76e685a76cc">More...</a><br/></td></tr>
<tr class="separator:ga7e39be0cb9e08f4c9231f76e685a76cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a61a9bf8e0b229925a5ddbf763b414b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga7a61a9bf8e0b229925a5ddbf763b414b">XSCUGIC_DISABLE_OFFSET</a>&#160;&#160;&#160;0x00000180U</td></tr>
<tr class="memdesc:ga7a61a9bf8e0b229925a5ddbf763b414b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Clear Register.  <a href="#ga7a61a9bf8e0b229925a5ddbf763b414b">More...</a><br/></td></tr>
<tr class="separator:ga7a61a9bf8e0b229925a5ddbf763b414b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf9985097ea7d040ad1eb0d1c45ade3f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gadf9985097ea7d040ad1eb0d1c45ade3f">XSCUGIC_PENDING_SET_OFFSET</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:gadf9985097ea7d040ad1eb0d1c45ade3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pending Set Register.  <a href="#gadf9985097ea7d040ad1eb0d1c45ade3f">More...</a><br/></td></tr>
<tr class="separator:gadf9985097ea7d040ad1eb0d1c45ade3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3bd893d8bffa293ebf525ff6fc580f82"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga3bd893d8bffa293ebf525ff6fc580f82">XSCUGIC_PENDING_CLR_OFFSET</a>&#160;&#160;&#160;0x00000280U</td></tr>
<tr class="memdesc:ga3bd893d8bffa293ebf525ff6fc580f82"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pending Clear Register.  <a href="#ga3bd893d8bffa293ebf525ff6fc580f82">More...</a><br/></td></tr>
<tr class="separator:ga3bd893d8bffa293ebf525ff6fc580f82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga522b8af56f229548a2360bdbedd7a6f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga522b8af56f229548a2360bdbedd7a6f3">XSCUGIC_ACTIVE_OFFSET</a>&#160;&#160;&#160;0x00000300U</td></tr>
<tr class="memdesc:ga522b8af56f229548a2360bdbedd7a6f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Active Status Register.  <a href="#ga522b8af56f229548a2360bdbedd7a6f3">More...</a><br/></td></tr>
<tr class="separator:ga522b8af56f229548a2360bdbedd7a6f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4e103b71357ac53c890d8aebd3b80997"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga4e103b71357ac53c890d8aebd3b80997">XSCUGIC_PRIORITY_OFFSET</a>&#160;&#160;&#160;0x00000400U</td></tr>
<tr class="memdesc:ga4e103b71357ac53c890d8aebd3b80997"><td class="mdescLeft">&#160;</td><td class="mdescRight">Priority Level Register.  <a href="#ga4e103b71357ac53c890d8aebd3b80997">More...</a><br/></td></tr>
<tr class="separator:ga4e103b71357ac53c890d8aebd3b80997"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ff09d2f6f8b9b89f847f756ee0ed408"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga0ff09d2f6f8b9b89f847f756ee0ed408">XSCUGIC_SPI_TARGET_OFFSET</a>&#160;&#160;&#160;0x00000800U</td></tr>
<tr class="memdesc:ga0ff09d2f6f8b9b89f847f756ee0ed408"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI Target Register 0x800-0x8FB.  <a href="#ga0ff09d2f6f8b9b89f847f756ee0ed408">More...</a><br/></td></tr>
<tr class="separator:ga0ff09d2f6f8b9b89f847f756ee0ed408"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c3e4a0e11aeeb05a7425826893a48b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga8c3e4a0e11aeeb05a7425826893a48b5">XSCUGIC_INT_CFG_OFFSET</a>&#160;&#160;&#160;0x00000C00U</td></tr>
<tr class="memdesc:ga8c3e4a0e11aeeb05a7425826893a48b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Configuration Register 0xC00-0xCFC.  <a href="#ga8c3e4a0e11aeeb05a7425826893a48b5">More...</a><br/></td></tr>
<tr class="separator:ga8c3e4a0e11aeeb05a7425826893a48b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b0239e9c600cc249f62309ca6ea7904"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga5b0239e9c600cc249f62309ca6ea7904">XSCUGIC_PPI_STAT_OFFSET</a>&#160;&#160;&#160;0x00000D00U</td></tr>
<tr class="memdesc:ga5b0239e9c600cc249f62309ca6ea7904"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status Register.  <a href="#ga5b0239e9c600cc249f62309ca6ea7904">More...</a><br/></td></tr>
<tr class="separator:ga5b0239e9c600cc249f62309ca6ea7904"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga809581b2c56e40481e49ba23535c4d52"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga809581b2c56e40481e49ba23535c4d52">XSCUGIC_SPI_STAT_OFFSET</a>&#160;&#160;&#160;0x00000D04U</td></tr>
<tr class="memdesc:ga809581b2c56e40481e49ba23535c4d52"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI Status Register 0xd04-0xd7C.  <a href="#ga809581b2c56e40481e49ba23535c4d52">More...</a><br/></td></tr>
<tr class="separator:ga809581b2c56e40481e49ba23535c4d52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d4a040ef70e7a3c49d3175dbb1eb381"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga0d4a040ef70e7a3c49d3175dbb1eb381">XSCUGIC_AHB_CONFIG_OFFSET</a>&#160;&#160;&#160;0x00000D80U</td></tr>
<tr class="memdesc:ga0d4a040ef70e7a3c49d3175dbb1eb381"><td class="mdescLeft">&#160;</td><td class="mdescRight">AHB Configuration Register.  <a href="#ga0d4a040ef70e7a3c49d3175dbb1eb381">More...</a><br/></td></tr>
<tr class="separator:ga0d4a040ef70e7a3c49d3175dbb1eb381"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5152b8067164fc0208df744dd20edea4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga5152b8067164fc0208df744dd20edea4">XSCUGIC_SFI_TRIG_OFFSET</a>&#160;&#160;&#160;0x00000F00U</td></tr>
<tr class="memdesc:ga5152b8067164fc0208df744dd20edea4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Software Triggered Interrupt Register.  <a href="#ga5152b8067164fc0208df744dd20edea4">More...</a><br/></td></tr>
<tr class="separator:ga5152b8067164fc0208df744dd20edea4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa933fc8e5812dcef2571db933c761d10"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaa933fc8e5812dcef2571db933c761d10">XSCUGIC_PERPHID_OFFSET</a>&#160;&#160;&#160;0x00000FD0U</td></tr>
<tr class="memdesc:gaa933fc8e5812dcef2571db933c761d10"><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral ID Reg.  <a href="#gaa933fc8e5812dcef2571db933c761d10">More...</a><br/></td></tr>
<tr class="separator:gaa933fc8e5812dcef2571db933c761d10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga41becddbff3dcc589f4c9d70d0177ff6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga41becddbff3dcc589f4c9d70d0177ff6">XSCUGIC_PCELLID_OFFSET</a>&#160;&#160;&#160;0x00000FF0U</td></tr>
<tr class="memdesc:ga41becddbff3dcc589f4c9d70d0177ff6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pcell ID Register.  <a href="#ga41becddbff3dcc589f4c9d70d0177ff6">More...</a><br/></td></tr>
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Distributor Enable Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp7af5973e746d6a6545c03ac1f4eea56c"></a>Controls if the distributor response to external interrupt inputs. </p>
</td></tr>
<tr class="memitem:gabd696b30c6257dea212cb9925ba73796"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gabd696b30c6257dea212cb9925ba73796">XSCUGIC_EN_INT_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gabd696b30c6257dea212cb9925ba73796"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt In Enable.  <a href="#gabd696b30c6257dea212cb9925ba73796">More...</a><br/></td></tr>
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Interrupt Controller Type Register</h2></td></tr>
<tr class="memitem:ga63c9b51176e1db04adbbfa91b517d9a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga63c9b51176e1db04adbbfa91b517d9a1">XSCUGIC_LSPI_MASK</a>&#160;&#160;&#160;0x0000F800U</td></tr>
<tr class="memdesc:ga63c9b51176e1db04adbbfa91b517d9a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Lockable Shared Peripheral Interrupts.  <a href="#ga63c9b51176e1db04adbbfa91b517d9a1">More...</a><br/></td></tr>
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<tr class="memitem:gaad0bd2ae20c2b47d8c7aaea2a78f5199"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaad0bd2ae20c2b47d8c7aaea2a78f5199">XSCUGIC_DOMAIN_MASK</a>&#160;&#160;&#160;0x00000400U</td></tr>
<tr class="memdesc:gaad0bd2ae20c2b47d8c7aaea2a78f5199"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number os Security domains.  <a href="#gaad0bd2ae20c2b47d8c7aaea2a78f5199">More...</a><br/></td></tr>
<tr class="separator:gaad0bd2ae20c2b47d8c7aaea2a78f5199"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21918105af9b486b28a8581c2caac127"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga21918105af9b486b28a8581c2caac127">XSCUGIC_CPU_NUM_MASK</a>&#160;&#160;&#160;0x000000E0U</td></tr>
<tr class="memdesc:ga21918105af9b486b28a8581c2caac127"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of CPU Interfaces.  <a href="#ga21918105af9b486b28a8581c2caac127">More...</a><br/></td></tr>
<tr class="separator:ga21918105af9b486b28a8581c2caac127"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e47c517a580a243cde47a69d1fe6d50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga5e47c517a580a243cde47a69d1fe6d50">XSCUGIC_NUM_INT_MASK</a>&#160;&#160;&#160;0x0000001FU</td></tr>
<tr class="memdesc:ga5e47c517a580a243cde47a69d1fe6d50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of Interrupt IDs.  <a href="#ga5e47c517a580a243cde47a69d1fe6d50">More...</a><br/></td></tr>
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Implementor ID Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp24bd6a8dfdab0f60a2f42c0049841673"></a>Implementor and revision information. </p>
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<tr class="memitem:ga0e4e42f499ef03373095daf342ffa988"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga0e4e42f499ef03373095daf342ffa988">XSCUGIC_REV_MASK</a>&#160;&#160;&#160;0x00FFF000U</td></tr>
<tr class="memdesc:ga0e4e42f499ef03373095daf342ffa988"><td class="mdescLeft">&#160;</td><td class="mdescRight">Revision Number.  <a href="#ga0e4e42f499ef03373095daf342ffa988">More...</a><br/></td></tr>
<tr class="separator:ga0e4e42f499ef03373095daf342ffa988"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab972b346f99c89c1913e6e49edc6fb0d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gab972b346f99c89c1913e6e49edc6fb0d">XSCUGIC_IMPL_MASK</a>&#160;&#160;&#160;0x00000FFFU</td></tr>
<tr class="memdesc:gab972b346f99c89c1913e6e49edc6fb0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Implementor.  <a href="#gab972b346f99c89c1913e6e49edc6fb0d">More...</a><br/></td></tr>
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Interrupt Security Registers</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp82bab760f7b03ebe2bc9d1f4e23a1a34"></a>Each bit controls the security level of an interrupt, either secure or non secure.</p>
<p>These registers can only be accessed using secure read and write. There are registers for each of the CPU interfaces at offset 0x080. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x084. </p>
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<tr class="memitem:gadd615bcd7723580422f99170f7beff31"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gadd615bcd7723580422f99170f7beff31">XSCUGIC_INT_NS_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gadd615bcd7723580422f99170f7beff31"><td class="mdescLeft">&#160;</td><td class="mdescRight">Each bit corresponds to an INT_ID.  <a href="#gadd615bcd7723580422f99170f7beff31">More...</a><br/></td></tr>
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Enable Set Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpfc9b79698fcc71d1c2c068023be25157"></a>Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is enabled.</p>
<p>Writing a 0 has no effect. Use the ENABLE_CLR register to set a bit to 0. There are registers for each of the CPU interfaces at offset 0x100. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x104. </p>
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<tr class="memitem:ga235b4d8d83653aae756d0377f6d42793"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga235b4d8d83653aae756d0377f6d42793">XSCUGIC_INT_EN_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga235b4d8d83653aae756d0377f6d42793"><td class="mdescLeft">&#160;</td><td class="mdescRight">Each bit corresponds to an INT_ID.  <a href="#ga235b4d8d83653aae756d0377f6d42793">More...</a><br/></td></tr>
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Enable Clear Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpd72f92b83e2ca87f274fcf5dc3202d2b"></a>Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is enabled.</p>
<p>Writing a 0 has no effect. Writing a 1 disables an interrupt and sets the corresponding bit to 0. There are registers for each of the CPU interfaces at offset 0x180. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x184. </p>
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<tr class="memitem:ga53b866f6da52f01e4e230217b92203e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga53b866f6da52f01e4e230217b92203e1">XSCUGIC_INT_CLR_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga53b866f6da52f01e4e230217b92203e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Each bit corresponds to an INT_ID.  <a href="#ga53b866f6da52f01e4e230217b92203e1">More...</a><br/></td></tr>
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Pending Set Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpc4b58cca2a0b76e63badbc015c3798f6"></a>Each bit controls the Pending or Active and Pending state of an interrupt, a 0 is not pending, a 1 is pending.</p>
<p>Writing a 0 has no effect. Writing a 1 sets an interrupt to the pending state. There are registers for each of the CPU interfaces at offset 0x200. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x204. </p>
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<tr class="memitem:gaf9f9e786eda7eaa92e2a2661b6ff194c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaf9f9e786eda7eaa92e2a2661b6ff194c">XSCUGIC_PEND_SET_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gaf9f9e786eda7eaa92e2a2661b6ff194c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Each bit corresponds to an INT_ID.  <a href="#gaf9f9e786eda7eaa92e2a2661b6ff194c">More...</a><br/></td></tr>
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Pending Clear Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp9d904fef526c1c8ed5983d7dcc68ac25"></a>Each bit can clear the Pending or Active and Pending state of an interrupt, a 0 is not pending, a 1 is pending.</p>
<p>Writing a 0 has no effect. Writing a 1 clears the pending state of an interrupt. There are registers for each of the CPU interfaces at offset 0x280. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x284. </p>
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<tr class="memitem:gac000c78a5731608de6ea4951fff8b7a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gac000c78a5731608de6ea4951fff8b7a5">XSCUGIC_PEND_CLR_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gac000c78a5731608de6ea4951fff8b7a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Each bit corresponds to an INT_ID.  <a href="#gac000c78a5731608de6ea4951fff8b7a5">More...</a><br/></td></tr>
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Active Status Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp60037005e550639fa11f4a1d53db08a2"></a>Each bit provides the Active status of an interrupt, a 0 is not Active, a 1 is Active.</p>
<p>This is a read only register. There are registers for each of the CPU interfaces at offset 0x300. With up to 8 registers aliased to each address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x380. </p>
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<tr class="memitem:ga8ffa809cf8e6e237833431b9e28e74b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga8ffa809cf8e6e237833431b9e28e74b6">XSCUGIC_ACTIVE_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga8ffa809cf8e6e237833431b9e28e74b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Each bit corresponds to an INT_ID.  <a href="#ga8ffa809cf8e6e237833431b9e28e74b6">More...</a><br/></td></tr>
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Priority Level Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpb3fecef3bdf77b787a87359346fe84cb"></a>Each byte in a Priority Level Register sets the priority level of an interrupt.</p>
<p>Reading the register provides the priority level of an interrupt. There are registers for each of the CPU interfaces at offset 0x400 through 0x41C. With up to 8 registers aliased to each address. 0 is highest priority, 0xFF is lowest. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 255 of these registers staring at location 0x420. </p>
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<tr class="memitem:gaf56426a8af8b676cb9184cf2196b6bf4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaf56426a8af8b676cb9184cf2196b6bf4">XSCUGIC_PRIORITY_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gaf56426a8af8b676cb9184cf2196b6bf4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Each Byte corresponds to an INT_ID.  <a href="#gaf56426a8af8b676cb9184cf2196b6bf4">More...</a><br/></td></tr>
<tr class="separator:gaf56426a8af8b676cb9184cf2196b6bf4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c2deb04ec9dad4c61b564f53b246ec0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga5c2deb04ec9dad4c61b564f53b246ec0">XSCUGIC_PRIORITY_MAX</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga5c2deb04ec9dad4c61b564f53b246ec0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Highest value of a priority actually the lowest priority.  <a href="#ga5c2deb04ec9dad4c61b564f53b246ec0">More...</a><br/></td></tr>
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SPI Target Register 0x800-0x8FB</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp255d77fe55965e1767d13a5419b4e42b"></a>Each byte references a separate SPI and programs which of the up to 8 CPU interfaces are sent a Pending interrupt.</p>
<p>There are registers for each of the CPU interfaces at offset 0x800 through 0x81C. With up to 8 registers aliased to each address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 255 of these registers staring at location 0x820.</p>
<p>This driver does not support multiple CPU interfaces. These are included for complete documentation. </p>
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<tr class="memitem:gade96daa17197385ab3071b1f46591d93"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gade96daa17197385ab3071b1f46591d93">XSCUGIC_SPI_CPU7_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:gade96daa17197385ab3071b1f46591d93"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU 7 Mask.  <a href="#gade96daa17197385ab3071b1f46591d93">More...</a><br/></td></tr>
<tr class="separator:gade96daa17197385ab3071b1f46591d93"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95ff6c51df6995c41ec8c8a4c2104cbd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga95ff6c51df6995c41ec8c8a4c2104cbd">XSCUGIC_SPI_CPU6_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga95ff6c51df6995c41ec8c8a4c2104cbd"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU 6 Mask.  <a href="#ga95ff6c51df6995c41ec8c8a4c2104cbd">More...</a><br/></td></tr>
<tr class="separator:ga95ff6c51df6995c41ec8c8a4c2104cbd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae004cb0d1b4d0f54646a1576c1054c43"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gae004cb0d1b4d0f54646a1576c1054c43">XSCUGIC_SPI_CPU5_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gae004cb0d1b4d0f54646a1576c1054c43"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU 5 Mask.  <a href="#gae004cb0d1b4d0f54646a1576c1054c43">More...</a><br/></td></tr>
<tr class="separator:gae004cb0d1b4d0f54646a1576c1054c43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8fc98206cf989c81b171719c0f590676"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga8fc98206cf989c81b171719c0f590676">XSCUGIC_SPI_CPU4_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:ga8fc98206cf989c81b171719c0f590676"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU 4 Mask.  <a href="#ga8fc98206cf989c81b171719c0f590676">More...</a><br/></td></tr>
<tr class="separator:ga8fc98206cf989c81b171719c0f590676"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa32beb32b38ed8d081dab55658db505b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaa32beb32b38ed8d081dab55658db505b">XSCUGIC_SPI_CPU3_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gaa32beb32b38ed8d081dab55658db505b"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU 3 Mask.  <a href="#gaa32beb32b38ed8d081dab55658db505b">More...</a><br/></td></tr>
<tr class="separator:gaa32beb32b38ed8d081dab55658db505b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8602b97c00f48225e1d7cc8d7ed5a7bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga8602b97c00f48225e1d7cc8d7ed5a7bb">XSCUGIC_SPI_CPU2_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga8602b97c00f48225e1d7cc8d7ed5a7bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU 2 Mask.  <a href="#ga8602b97c00f48225e1d7cc8d7ed5a7bb">More...</a><br/></td></tr>
<tr class="separator:ga8602b97c00f48225e1d7cc8d7ed5a7bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5acd0af7b918d410b4c95853f7b8c959"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga5acd0af7b918d410b4c95853f7b8c959">XSCUGIC_SPI_CPU1_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga5acd0af7b918d410b4c95853f7b8c959"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU 1 Mask.  <a href="#ga5acd0af7b918d410b4c95853f7b8c959">More...</a><br/></td></tr>
<tr class="separator:ga5acd0af7b918d410b4c95853f7b8c959"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6958ba672ad449aa981f7fae9412455"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaf6958ba672ad449aa981f7fae9412455">XSCUGIC_SPI_CPU0_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gaf6958ba672ad449aa981f7fae9412455"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU 0 Mask.  <a href="#gaf6958ba672ad449aa981f7fae9412455">More...</a><br/></td></tr>
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Interrupt Configuration Register 0xC00-0xCFC</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpa294e9d8bc87019d409c405039433b40"></a>The interrupt configuration registers program an SFI to be active HIGH level sensitive or rising edge sensitive.</p>
<p>Each bit pair describes the configuration for an INT_ID. SFI Read Only b10 always PPI Read Only depending on how the PPIs are configured. b01 Active HIGH level sensitive b11 Rising edge sensitive SPI LSB is read only. b01 Active HIGH level sensitive b11 Rising edge sensitive/ There are registers for each of the CPU interfaces at offset 0xC00 through 0xC04. With up to 8 registers aliased to each address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 255 of these registers staring at location 0xC08. </p>
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<tr class="memitem:ga2be546274013a123da9a0a8f21acfbc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga2be546274013a123da9a0a8f21acfbc5">XSCUGIC_INT_CFG_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga2be546274013a123da9a0a8f21acfbc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt configuration Mask.  <a href="#ga2be546274013a123da9a0a8f21acfbc5">More...</a><br/></td></tr>
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PPI Status Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp562f0278b12405f008e33684ce0d92f6"></a>Enables an external AMBA master to access the status of the PPI inputs.</p>
<p>A CPU can only read the status of its local PPI signals and cannot read the status for other CPUs. This register is aliased for each CPU interface. </p>
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<tr class="memitem:ga7fb6f58522fbce60a5d8e51ade739208"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga7fb6f58522fbce60a5d8e51ade739208">XSCUGIC_PPI_C15_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:ga7fb6f58522fbce60a5d8e51ade739208"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#ga7fb6f58522fbce60a5d8e51ade739208">More...</a><br/></td></tr>
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<tr class="memitem:ga6797b4c956ee74df8c35314ce817cc32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga6797b4c956ee74df8c35314ce817cc32">XSCUGIC_PPI_C14_MASK</a>&#160;&#160;&#160;0x00004000U</td></tr>
<tr class="memdesc:ga6797b4c956ee74df8c35314ce817cc32"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#ga6797b4c956ee74df8c35314ce817cc32">More...</a><br/></td></tr>
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<tr class="memitem:gacc7fa22af93b8377b1f757d83a1a47a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gacc7fa22af93b8377b1f757d83a1a47a4">XSCUGIC_PPI_C13_MASK</a>&#160;&#160;&#160;0x00002000U</td></tr>
<tr class="memdesc:gacc7fa22af93b8377b1f757d83a1a47a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#gacc7fa22af93b8377b1f757d83a1a47a4">More...</a><br/></td></tr>
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<tr class="memitem:gabd6aceee4c3c462bc1a9f95495d17181"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gabd6aceee4c3c462bc1a9f95495d17181">XSCUGIC_PPI_C12_MASK</a>&#160;&#160;&#160;0x00001000U</td></tr>
<tr class="memdesc:gabd6aceee4c3c462bc1a9f95495d17181"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#gabd6aceee4c3c462bc1a9f95495d17181">More...</a><br/></td></tr>
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<tr class="memitem:ga8318aad85340f5318de41b98da04100c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga8318aad85340f5318de41b98da04100c">XSCUGIC_PPI_C11_MASK</a>&#160;&#160;&#160;0x00000800U</td></tr>
<tr class="memdesc:ga8318aad85340f5318de41b98da04100c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#ga8318aad85340f5318de41b98da04100c">More...</a><br/></td></tr>
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<tr class="memitem:ga7a0c40850819f2d48d9ccaa274cd4881"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga7a0c40850819f2d48d9ccaa274cd4881">XSCUGIC_PPI_C10_MASK</a>&#160;&#160;&#160;0x00000400U</td></tr>
<tr class="memdesc:ga7a0c40850819f2d48d9ccaa274cd4881"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#ga7a0c40850819f2d48d9ccaa274cd4881">More...</a><br/></td></tr>
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<tr class="memitem:ga5a79ff73cc31e2233f58a682a9421c5d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga5a79ff73cc31e2233f58a682a9421c5d">XSCUGIC_PPI_C09_MASK</a>&#160;&#160;&#160;0x00000200U</td></tr>
<tr class="memdesc:ga5a79ff73cc31e2233f58a682a9421c5d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#ga5a79ff73cc31e2233f58a682a9421c5d">More...</a><br/></td></tr>
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<tr class="memitem:ga98cf40b1bb6de7edfe1034883780eb51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga98cf40b1bb6de7edfe1034883780eb51">XSCUGIC_PPI_C08_MASK</a>&#160;&#160;&#160;0x00000100U</td></tr>
<tr class="memdesc:ga98cf40b1bb6de7edfe1034883780eb51"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#ga98cf40b1bb6de7edfe1034883780eb51">More...</a><br/></td></tr>
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<tr class="memitem:gac9103c688cb9f66402d43acdce1ec2d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gac9103c688cb9f66402d43acdce1ec2d4">XSCUGIC_PPI_C07_MASK</a>&#160;&#160;&#160;0x00000080U</td></tr>
<tr class="memdesc:gac9103c688cb9f66402d43acdce1ec2d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#gac9103c688cb9f66402d43acdce1ec2d4">More...</a><br/></td></tr>
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<tr class="memitem:gab4746833af92bb2cd60f47c5aef3c412"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gab4746833af92bb2cd60f47c5aef3c412">XSCUGIC_PPI_C06_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:gab4746833af92bb2cd60f47c5aef3c412"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#gab4746833af92bb2cd60f47c5aef3c412">More...</a><br/></td></tr>
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<tr class="memitem:gaddc4c3db586fa77620204fc196c79196"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaddc4c3db586fa77620204fc196c79196">XSCUGIC_PPI_C05_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gaddc4c3db586fa77620204fc196c79196"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#gaddc4c3db586fa77620204fc196c79196">More...</a><br/></td></tr>
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<tr class="memitem:gafb35a04b39200dc2531978c5b819a05f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gafb35a04b39200dc2531978c5b819a05f">XSCUGIC_PPI_C04_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gafb35a04b39200dc2531978c5b819a05f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#gafb35a04b39200dc2531978c5b819a05f">More...</a><br/></td></tr>
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<tr class="memitem:ga1227f27b3f3566c377741ed4500864eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga1227f27b3f3566c377741ed4500864eb">XSCUGIC_PPI_C03_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga1227f27b3f3566c377741ed4500864eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#ga1227f27b3f3566c377741ed4500864eb">More...</a><br/></td></tr>
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<tr class="memitem:ga841e2da3b34252affcbe1ae420dee5cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga841e2da3b34252affcbe1ae420dee5cd">XSCUGIC_PPI_C02_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga841e2da3b34252affcbe1ae420dee5cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#ga841e2da3b34252affcbe1ae420dee5cd">More...</a><br/></td></tr>
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<tr class="memitem:gaa6af05ff49c40b1f95ddef70720c661d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaa6af05ff49c40b1f95ddef70720c661d">XSCUGIC_PPI_C01_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gaa6af05ff49c40b1f95ddef70720c661d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#gaa6af05ff49c40b1f95ddef70720c661d">More...</a><br/></td></tr>
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<tr class="memitem:gab0d1549e1fdc4ee0efda5b9a7d19f1c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gab0d1549e1fdc4ee0efda5b9a7d19f1c9">XSCUGIC_PPI_C00_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gab0d1549e1fdc4ee0efda5b9a7d19f1c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">PPI Status.  <a href="#gab0d1549e1fdc4ee0efda5b9a7d19f1c9">More...</a><br/></td></tr>
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SPI Status Register 0xd04-0xd7C</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpebacc84cc2901590e0b1e59c1093f58a"></a>Enables an external AMBA master to access the status of the SPI inputs.</p>
<p>There are up to 63 registers if the maximum number of SPI inputs are configured. </p>
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<tr class="memitem:ga06ee88cda2455e25cd6c1d5b4d7eb7b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga06ee88cda2455e25cd6c1d5b4d7eb7b3">XSCUGIC_SPI_N_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga06ee88cda2455e25cd6c1d5b4d7eb7b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Each bit corresponds to an SPI input.  <a href="#ga06ee88cda2455e25cd6c1d5b4d7eb7b3">More...</a><br/></td></tr>
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AHB Configuration Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp20e708e8b6f9515a11e4374915be812a"></a>Provides the status of the CFGBIGEND input signal and allows the endianness of the GIC to be set. </p>
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<tr class="memitem:ga3b4028834925dd0ed1a6175492d8ae89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga3b4028834925dd0ed1a6175492d8ae89">XSCUGIC_AHB_END_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga3b4028834925dd0ed1a6175492d8ae89"><td class="mdescLeft">&#160;</td><td class="mdescRight">0-GIC uses little Endian, 1-GIC uses Big Endian  <a href="#ga3b4028834925dd0ed1a6175492d8ae89">More...</a><br/></td></tr>
<tr class="separator:ga3b4028834925dd0ed1a6175492d8ae89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa9d9d58262a639eb2a8858e2856b277d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaa9d9d58262a639eb2a8858e2856b277d">XSCUGIC_AHB_ENDOVR_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gaa9d9d58262a639eb2a8858e2856b277d"><td class="mdescLeft">&#160;</td><td class="mdescRight">0-Uses CFGBIGEND control, 1-use the AHB_END bit  <a href="#gaa9d9d58262a639eb2a8858e2856b277d">More...</a><br/></td></tr>
<tr class="separator:gaa9d9d58262a639eb2a8858e2856b277d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga786c66ef9c8619b0a36ae25e85ea58e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga786c66ef9c8619b0a36ae25e85ea58e5">XSCUGIC_AHB_TIE_OFF_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga786c66ef9c8619b0a36ae25e85ea58e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">State of CFGBIGEND.  <a href="#ga786c66ef9c8619b0a36ae25e85ea58e5">More...</a><br/></td></tr>
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Software Triggered Interrupt Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpbd6bfc65d0173bfbdf245b7425cb5dc7"></a>Controls issuing of software interrupts. </p>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSCUGIC_SFI_SELFTRIG_MASK</b>&#160;&#160;&#160;0x02010000U</td></tr>
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<tr class="memitem:ga57d7eef981cdc87055eb0df1d147a822"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga57d7eef981cdc87055eb0df1d147a822">XSCUGIC_SFI_TRIG_TRGFILT_MASK</a>&#160;&#160;&#160;0x03000000U</td></tr>
<tr class="memdesc:ga57d7eef981cdc87055eb0df1d147a822"><td class="mdescLeft">&#160;</td><td class="mdescRight">Target List filter b00-Use the target List b01-All CPUs except requester b10-To Requester b11-reserved.  <a href="#ga57d7eef981cdc87055eb0df1d147a822">More...</a><br/></td></tr>
<tr class="separator:ga57d7eef981cdc87055eb0df1d147a822"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab68476cc3813858c0c809ebfb4e28c74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gab68476cc3813858c0c809ebfb4e28c74">XSCUGIC_SFI_TRIG_CPU_MASK</a>&#160;&#160;&#160;0x00FF0000U</td></tr>
<tr class="memdesc:gab68476cc3813858c0c809ebfb4e28c74"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU Target list.  <a href="#gab68476cc3813858c0c809ebfb4e28c74">More...</a><br/></td></tr>
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<tr class="memitem:ga14c75b6deed6c34d98453d802627a26e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga14c75b6deed6c34d98453d802627a26e">XSCUGIC_SFI_TRIG_SATT_MASK</a>&#160;&#160;&#160;0x00008000U</td></tr>
<tr class="memdesc:ga14c75b6deed6c34d98453d802627a26e"><td class="mdescLeft">&#160;</td><td class="mdescRight">0= Use a secure interrupt  <a href="#ga14c75b6deed6c34d98453d802627a26e">More...</a><br/></td></tr>
<tr class="separator:ga14c75b6deed6c34d98453d802627a26e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7956d8a2796ad6f92fafc49d92aa1a7d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga7956d8a2796ad6f92fafc49d92aa1a7d">XSCUGIC_SFI_TRIG_INTID_MASK</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:ga7956d8a2796ad6f92fafc49d92aa1a7d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set to the INTID signaled to the CPU.  <a href="#ga7956d8a2796ad6f92fafc49d92aa1a7d">More...</a><br/></td></tr>
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CPU Interface Register Map</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpae7a7a841f30e81a731ad01209d34189"></a>Define the offsets from the base address for all CPU registers of the interrupt controller, some registers may be reserved in the hardware device. </p>
</td></tr>
<tr class="memitem:gadc15f5222681d55b9c1d391b067d37fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gadc15f5222681d55b9c1d391b067d37fa">XSCUGIC_CONTROL_OFFSET</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:gadc15f5222681d55b9c1d391b067d37fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU Interface Control Register.  <a href="#gadc15f5222681d55b9c1d391b067d37fa">More...</a><br/></td></tr>
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<tr class="memitem:ga924ad35e75dc4788443bee4dc2d1e61e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga924ad35e75dc4788443bee4dc2d1e61e">XSCUGIC_CPU_PRIOR_OFFSET</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga924ad35e75dc4788443bee4dc2d1e61e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Priority Mask Reg.  <a href="#ga924ad35e75dc4788443bee4dc2d1e61e">More...</a><br/></td></tr>
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<tr class="memitem:gab0aa4aa9a2e2b9af2b654967f387dd2c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gab0aa4aa9a2e2b9af2b654967f387dd2c">XSCUGIC_BIN_PT_OFFSET</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gab0aa4aa9a2e2b9af2b654967f387dd2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Binary Point Register.  <a href="#gab0aa4aa9a2e2b9af2b654967f387dd2c">More...</a><br/></td></tr>
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<tr class="memitem:ga5f1418c8f0e05b7f928c2fff42b4514d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga5f1418c8f0e05b7f928c2fff42b4514d">XSCUGIC_INT_ACK_OFFSET</a>&#160;&#160;&#160;0x0000000CU</td></tr>
<tr class="memdesc:ga5f1418c8f0e05b7f928c2fff42b4514d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt ACK Reg.  <a href="#ga5f1418c8f0e05b7f928c2fff42b4514d">More...</a><br/></td></tr>
<tr class="separator:ga5f1418c8f0e05b7f928c2fff42b4514d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa65c329712b1a7f3ab12b0bf4ada058d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaa65c329712b1a7f3ab12b0bf4ada058d">XSCUGIC_EOI_OFFSET</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gaa65c329712b1a7f3ab12b0bf4ada058d"><td class="mdescLeft">&#160;</td><td class="mdescRight">End of Interrupt Reg.  <a href="#gaa65c329712b1a7f3ab12b0bf4ada058d">More...</a><br/></td></tr>
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<tr class="memitem:ga9032b8ad311f376fd5d8fc046e4032f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga9032b8ad311f376fd5d8fc046e4032f4">XSCUGIC_RUN_PRIOR_OFFSET</a>&#160;&#160;&#160;0x00000014U</td></tr>
<tr class="memdesc:ga9032b8ad311f376fd5d8fc046e4032f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Running Priority Reg.  <a href="#ga9032b8ad311f376fd5d8fc046e4032f4">More...</a><br/></td></tr>
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<tr class="memitem:gaa8f4426fddda8466c267b661457dd54e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaa8f4426fddda8466c267b661457dd54e">XSCUGIC_HI_PEND_OFFSET</a>&#160;&#160;&#160;0x00000018U</td></tr>
<tr class="memdesc:gaa8f4426fddda8466c267b661457dd54e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Highest Pending Interrupt Register.  <a href="#gaa8f4426fddda8466c267b661457dd54e">More...</a><br/></td></tr>
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<tr class="memitem:ga8ca0e14be574b074b47ef33108794ca1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga8ca0e14be574b074b47ef33108794ca1">XSCUGIC_ALIAS_BIN_PT_OFFSET</a>&#160;&#160;&#160;0x0000001CU</td></tr>
<tr class="memdesc:ga8ca0e14be574b074b47ef33108794ca1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Aliased non-Secure Binary Point Register.  <a href="#ga8ca0e14be574b074b47ef33108794ca1">More...</a><br/></td></tr>
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Control Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp51793cbea2ebce2243b8f2115ce2db60"></a>CPU Interface Control register definitions All bits are defined here although some are not available in the non-secure mode. </p>
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<tr class="memitem:gab30530d436aee9b8fe1df9e0ddc9ac90"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gab30530d436aee9b8fe1df9e0ddc9ac90">XSCUGIC_CNTR_SBPR_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gab30530d436aee9b8fe1df9e0ddc9ac90"><td class="mdescLeft">&#160;</td><td class="mdescRight">Secure Binary Pointer, 0=separate registers, 1=both use bin_pt_s.  <a href="#gab30530d436aee9b8fe1df9e0ddc9ac90">More...</a><br/></td></tr>
<tr class="separator:gab30530d436aee9b8fe1df9e0ddc9ac90"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa696959041b1e0b4c5008c9fbf25a8b2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaa696959041b1e0b4c5008c9fbf25a8b2">XSCUGIC_CNTR_FIQEN_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:gaa696959041b1e0b4c5008c9fbf25a8b2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Use nFIQ_C for secure interrupts, 0= use IRQ for both, 1=Use FIQ for secure, IRQ for non.  <a href="#gaa696959041b1e0b4c5008c9fbf25a8b2">More...</a><br/></td></tr>
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<tr class="memitem:ga24146dc008dc9a9d8b76fb802bf843ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga24146dc008dc9a9d8b76fb802bf843ab">XSCUGIC_CNTR_ACKCTL_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga24146dc008dc9a9d8b76fb802bf843ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Ack control for secure or non secure.  <a href="#ga24146dc008dc9a9d8b76fb802bf843ab">More...</a><br/></td></tr>
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<tr class="memitem:ga95e109eaaa18f39f1525967987bb5167"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga95e109eaaa18f39f1525967987bb5167">XSCUGIC_CNTR_EN_NS_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga95e109eaaa18f39f1525967987bb5167"><td class="mdescLeft">&#160;</td><td class="mdescRight">Non Secure enable.  <a href="#ga95e109eaaa18f39f1525967987bb5167">More...</a><br/></td></tr>
<tr class="separator:ga95e109eaaa18f39f1525967987bb5167"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaea986d126fc3cf6efc9cdc86e347475"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gaaea986d126fc3cf6efc9cdc86e347475">XSCUGIC_CNTR_EN_S_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gaaea986d126fc3cf6efc9cdc86e347475"><td class="mdescLeft">&#160;</td><td class="mdescRight">Secure enable, 0=Disabled, 1=Enabled.  <a href="#gaaea986d126fc3cf6efc9cdc86e347475">More...</a><br/></td></tr>
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Binary Point Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp91554e07a5908b2b699a422c6bb97528"></a>Binary Point register definitions </p>
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<tr class="memitem:gabb83f3fd04a69ac1f7ace985db677e63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gabb83f3fd04a69ac1f7ace985db677e63">XSCUGIC_BIN_PT_MASK</a>&#160;&#160;&#160;0x00000007U</td></tr>
<tr class="memdesc:gabb83f3fd04a69ac1f7ace985db677e63"><td class="mdescLeft">&#160;</td><td class="mdescRight">Binary point mask value Value Secure Non-secure b000 0xFE 0xFF b001 0xFC 0xFE b010 0xF8 0xFC b011 0xF0 0xF8 b100 0xE0 0xF0 b101 0xC0 0xE0 b110 0x80 0xC0 b111 0x00 0x80.  <a href="#gabb83f3fd04a69ac1f7ace985db677e63">More...</a><br/></td></tr>
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Interrupt Acknowledge Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp8425d631a2f24338837b7f7e7727b794"></a>Interrupt Acknowledge register definitions Identifies the current Pending interrupt, and the CPU ID for software interrupts. </p>
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<tr class="memitem:gad9945cea79930d883f977fc97e1aa292"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gad9945cea79930d883f977fc97e1aa292">XSCUGIC_ACK_INTID_MASK</a>&#160;&#160;&#160;0x000003FFU</td></tr>
<tr class="memdesc:gad9945cea79930d883f977fc97e1aa292"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt ID.  <a href="#gad9945cea79930d883f977fc97e1aa292">More...</a><br/></td></tr>
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<tr class="memitem:ga3ea14a0a5360cd67164dc801ef1d7e3d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga3ea14a0a5360cd67164dc801ef1d7e3d">XSCUGIC_CPUID_MASK</a>&#160;&#160;&#160;0x00000C00U</td></tr>
<tr class="memdesc:ga3ea14a0a5360cd67164dc801ef1d7e3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">CPU ID.  <a href="#ga3ea14a0a5360cd67164dc801ef1d7e3d">More...</a><br/></td></tr>
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End of Interrupt Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp00db184b9c2eb15ec4bd536ea8ff1a45"></a>End of Interrupt register definitions Allows the CPU to signal the GIC when it completes an interrupt service routine. </p>
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<tr class="memitem:gad50524a3c9f6edaac90d6fa47907ec10"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#gad50524a3c9f6edaac90d6fa47907ec10">XSCUGIC_EOI_INTID_MASK</a>&#160;&#160;&#160;0x000003FFU</td></tr>
<tr class="memdesc:gad50524a3c9f6edaac90d6fa47907ec10"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt ID.  <a href="#gad50524a3c9f6edaac90d6fa47907ec10">More...</a><br/></td></tr>
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Running Priority Register</h2></td></tr>
<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp3d74eec3dffd27ef9c18a71f816cd30b"></a>Running Priority register definitions Identifies the interrupt priority level of the highest priority active interrupt. </p>
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<tr class="memitem:ga8ac1ba33bfaefe69aacd6221b0375f1c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__api.html#ga8ac1ba33bfaefe69aacd6221b0375f1c">XSCUGIC_RUN_PRIORITY_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:ga8ac1ba33bfaefe69aacd6221b0375f1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Priority.  <a href="#ga8ac1ba33bfaefe69aacd6221b0375f1c">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ga3dde6ae31d569b01dc88903a5340d744"></a>
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          <td class="memname">#define ARMA9</td>
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<p>ARMA9 macro to identify cortexA9. </p>

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          <td class="memname">#define DEFAULT_PRIORITY&#160;&#160;&#160;0xa0a0a0a0U</td>
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<p>Default value for priority_level register. </p>

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<p>Default value for priority_level register. </p>

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          <td class="memname">#define XSCUGIC_ACK_INTID_MASK&#160;&#160;&#160;0x000003FFU</td>
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<p>Interrupt ID. </p>

<p>Referenced by <a class="el" href="xscugic__low__level__example_8c.html#aa19b6eafe395a9ce4b9459234b832279">LowInterruptHandler()</a>, <a class="el" href="group__scugic__api.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler()</a>, and <a class="el" href="group__scugic__api.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>.</p>

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<a class="anchor" id="ga8ffa809cf8e6e237833431b9e28e74b6"></a>
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          <td class="memname">#define XSCUGIC_ACTIVE_MASK&#160;&#160;&#160;0x00000001U</td>
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<p>Each bit corresponds to an INT_ID. </p>

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          <td class="memname">#define XSCUGIC_ACTIVE_OFFSET&#160;&#160;&#160;0x00000300U</td>
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<p>Active Status Register. </p>

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          <td class="memname">#define XSCUGIC_AHB_CONFIG_OFFSET&#160;&#160;&#160;0x00000D80U</td>
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<p>AHB Configuration Register. </p>

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          <td class="memname">#define XSCUGIC_AHB_END_MASK&#160;&#160;&#160;0x00000004U</td>
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<p>0-GIC uses little Endian, 1-GIC uses Big Endian </p>

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          <td class="memname">#define XSCUGIC_AHB_ENDOVR_MASK&#160;&#160;&#160;0x00000002U</td>
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<p>0-Uses CFGBIGEND control, 1-use the AHB_END bit </p>

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          <td class="memname">#define XSCUGIC_AHB_TIE_OFF_MASK&#160;&#160;&#160;0x00000001U</td>
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<p>State of CFGBIGEND. </p>

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          <td class="memname">#define XSCUGIC_ALIAS_BIN_PT_OFFSET&#160;&#160;&#160;0x0000001CU</td>
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<p>Aliased non-Secure Binary Point Register. </p>
<p>0x00000020 to 0x00000FBC are reserved and should not be read or written to. </p>

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          <td class="memname">#define XSCUGIC_BIN_PT_MASK&#160;&#160;&#160;0x00000007U</td>
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<p>Binary point mask value Value Secure Non-secure b000 0xFE 0xFF b001 0xFC 0xFE b010 0xF8 0xFC b011 0xF0 0xF8 b100 0xE0 0xF0 b101 0xC0 0xE0 b110 0x80 0xC0 b111 0x00 0x80. </p>

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<a class="anchor" id="gab0aa4aa9a2e2b9af2b654967f387dd2c"></a>
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          <td class="memname">#define XSCUGIC_BIN_PT_OFFSET&#160;&#160;&#160;0x00000008U</td>
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<p>Binary Point Register. </p>

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          <td class="memname">#define XSCUGIC_CNTR_ACKCTL_MASK&#160;&#160;&#160;0x00000004U</td>
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<p>Ack control for secure or non secure. </p>

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          <td class="memname">#define XSCUGIC_CNTR_EN_NS_MASK&#160;&#160;&#160;0x00000002U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Non Secure enable. </p>

</div>
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          <td class="memname">#define XSCUGIC_CNTR_EN_S_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Secure enable, 0=Disabled, 1=Enabled. </p>

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<a class="anchor" id="gaa696959041b1e0b4c5008c9fbf25a8b2"></a>
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          <td class="memname">#define XSCUGIC_CNTR_FIQEN_MASK&#160;&#160;&#160;0x00000008U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Use nFIQ_C for secure interrupts, 0= use IRQ for both, 1=Use FIQ for secure, IRQ for non. </p>

</div>
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<a class="anchor" id="gab30530d436aee9b8fe1df9e0ddc9ac90"></a>
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          <td class="memname">#define XSCUGIC_CNTR_SBPR_MASK&#160;&#160;&#160;0x00000010U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Secure Binary Pointer, 0=separate registers, 1=both use bin_pt_s. </p>

</div>
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<a class="anchor" id="gadc15f5222681d55b9c1d391b067d37fa"></a>
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          <td class="memname">#define XSCUGIC_CONTROL_OFFSET&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>CPU Interface Control Register. </p>

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<a class="anchor" id="ga21918105af9b486b28a8581c2caac127"></a>
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<div class="memproto">
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          <td class="memname">#define XSCUGIC_CPU_NUM_MASK&#160;&#160;&#160;0x000000E0U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Number of CPU Interfaces. </p>

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<a class="anchor" id="ga924ad35e75dc4788443bee4dc2d1e61e"></a>
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<div class="memproto">
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          <td class="memname">#define XSCUGIC_CPU_PRIOR_OFFSET&#160;&#160;&#160;0x00000004U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Priority Mask Reg. </p>

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<a class="anchor" id="ga3ea14a0a5360cd67164dc801ef1d7e3d"></a>
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          <td class="memname">#define XSCUGIC_CPUID_MASK&#160;&#160;&#160;0x00000C00U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>CPU ID. </p>

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<a class="anchor" id="ga2f3bba7c5247812158ef4fde7a0e7dfe"></a>
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          <td class="memname">#define XScuGic_CPUReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(<a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>(((InstancePtr)-&gt;Config-&gt;CpuBaseAddress), (RegOffset)))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reads the given CPU Interface register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>Rregister offset to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>32-bit value of the register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__scugic__api.html#ga2f3bba7c5247812158ef4fde7a0e7dfe" title="Reads the given CPU Interface register. ">XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>.</p>

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<a class="anchor" id="ga2a4ba236ff7bfeab20b5ca81082f2b13"></a>
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          <td class="memname">#define XScuGic_CPUWriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>(((InstancePtr)-&gt;Config-&gt;CpuBaseAddress), (RegOffset), \</div>
<div class="line">                                        ((u32)(Data))))</div>
<div class="ttc" id="xscugic__hw_8h_html_a01c0f85e48858531c313ce22cbfd2dfa"><div class="ttname"><a href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a></div><div class="ttdeci">#define XScuGic_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Writes the given Intc register. </div><div class="ttdef"><b>Definition:</b> xscugic_hw.h:786</div></div>
</div><!-- fragment -->
<p>Writes the given CPU Interface register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>Register offset to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>32-bit value to write to the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__scugic__api.html#ga2a4ba236ff7bfeab20b5ca81082f2b13" title="Writes the given CPU Interface register. ">XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>.</p>

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<a class="anchor" id="ga7a61a9bf8e0b229925a5ddbf763b414b"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSCUGIC_DISABLE_OFFSET&#160;&#160;&#160;0x00000180U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable Clear Register. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaafd153e16238a1189c513846675e096a">XScuGic_Disable()</a>, <a class="el" href="group__scugic__api.html#ga0d183d23d05aac5d61cd640c5b39b275">XScuGic_DisableIntr()</a>, <a class="el" href="group__scugic__api.html#gad162acedbbd41fd890fc7f2225ed480b">XScuGic_Disconnect()</a>, and <a class="el" href="group__scugic__api.html#ga6146a0489a1c748ceeaee729639d48a7">XScuGic_Stop()</a>.</p>

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<a class="anchor" id="ga94cd5e2c3a1ab5b6c282d76bead5d616"></a>
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<div class="memproto">
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          <td class="memname">#define XSCUGIC_DIST_EN_OFFSET&#160;&#160;&#160;0x00000000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Distributor Enable Register. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga72b9aec992716861e5f0929e4d0d9f7c">XScuGic_IsInitialized()</a>, and <a class="el" href="group__scugic__api.html#ga6146a0489a1c748ceeaee729639d48a7">XScuGic_Stop()</a>.</p>

</div>
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<a class="anchor" id="gaff73afc08cc167202d5aac6661ae6a1e"></a>
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<div class="memproto">
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          <td class="memname">#define XSCUGIC_DIST_IDENT_OFFSET&#160;&#160;&#160;0x00000008U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Implementor ID Register. </p>

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<a class="anchor" id="ga3d639fe1851f9d833367fb4322390eeb"></a>
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          <td class="memname">#define XScuGic_DistReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(<a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>(((InstancePtr)-&gt;Config-&gt;DistBaseAddress), (RegOffset)))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reads the given Distributor Interface register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>Register offset to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="group__scugic__api.html#ga3d639fe1851f9d833367fb4322390eeb" title="Reads the given Distributor Interface register. ">XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType()</a>, <a class="el" href="group__scugic__api.html#ga2a94f1a519d965f051d598e5a6b5a855">XScuGic_InterruptMaptoCpu()</a>, <a class="el" href="group__scugic__api.html#ga04f8ea74458251784b293e4ad98f2d74">XScuGic_InterruptUnmapFromCpu()</a>, <a class="el" href="group__scugic__api.html#ga081a9a62546b413d94e609894282a575">XScuGic_SelfTest()</a>, <a class="el" href="group__scugic__api.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, <a class="el" href="group__scugic__api.html#ga6146a0489a1c748ceeaee729639d48a7">XScuGic_Stop()</a>, and <a class="el" href="group__scugic__api.html#ga66b2416be64a5e582e530ed9ed7f962c">XScuGic_UnmapAllInterruptsFromCpu()</a>.</p>

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<a class="anchor" id="ga22e9f81ed00f7cc39df1c6e76988fdb1"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XScuGic_DistWriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>(((InstancePtr)-&gt;Config-&gt;DistBaseAddress), (RegOffset), \</div>
<div class="line">                                        ((u32)(Data))))</div>
<div class="ttc" id="xscugic__hw_8h_html_a01c0f85e48858531c313ce22cbfd2dfa"><div class="ttname"><a href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a></div><div class="ttdeci">#define XScuGic_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Writes the given Intc register. </div><div class="ttdef"><b>Definition:</b> xscugic_hw.h:786</div></div>
</div><!-- fragment -->
<p>Writes the given Distributor Interface register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>Register offset to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>32-bit value to write to the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1" title="Writes the given Distributor Interface register. ">XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaafd153e16238a1189c513846675e096a">XScuGic_Disable()</a>, <a class="el" href="group__scugic__api.html#gad162acedbbd41fd890fc7f2225ed480b">XScuGic_Disconnect()</a>, <a class="el" href="group__scugic__api.html#gac965b9e3ae7668a92cf07a65bde142cc">XScuGic_Enable()</a>, <a class="el" href="group__scugic__api.html#ga2a94f1a519d965f051d598e5a6b5a855">XScuGic_InterruptMaptoCpu()</a>, <a class="el" href="group__scugic__api.html#ga04f8ea74458251784b293e4ad98f2d74">XScuGic_InterruptUnmapFromCpu()</a>, <a class="el" href="group__scugic__api.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, <a class="el" href="group__scugic__api.html#gaca28a576540ab5fcd75cee1f38917ae4">XScuGic_SoftwareIntr()</a>, <a class="el" href="group__scugic__api.html#ga6146a0489a1c748ceeaee729639d48a7">XScuGic_Stop()</a>, and <a class="el" href="group__scugic__api.html#ga66b2416be64a5e582e530ed9ed7f962c">XScuGic_UnmapAllInterruptsFromCpu()</a>.</p>

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<a class="anchor" id="gaad0bd2ae20c2b47d8c7aaea2a78f5199"></a>
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<div class="memproto">
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          <td class="memname">#define XSCUGIC_DOMAIN_MASK&#160;&#160;&#160;0x00000400U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Number os Security domains. </p>

</div>
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<a class="anchor" id="gabd696b30c6257dea212cb9925ba73796"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_EN_INT_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt In Enable. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga72b9aec992716861e5f0929e4d0d9f7c">XScuGic_IsInitialized()</a>, and <a class="el" href="group__scugic__api.html#ga6146a0489a1c748ceeaee729639d48a7">XScuGic_Stop()</a>.</p>

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</div>
<a class="anchor" id="ga7e39be0cb9e08f4c9231f76e685a76cc"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_ENABLE_SET_OFFSET&#160;&#160;&#160;0x00000100U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable Set Register. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gac965b9e3ae7668a92cf07a65bde142cc">XScuGic_Enable()</a>, and <a class="el" href="group__scugic__api.html#gadaa95193630e661a6a578f35a5e3ea1a">XScuGic_EnableIntr()</a>.</p>

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<a class="anchor" id="gad50524a3c9f6edaac90d6fa47907ec10"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_EOI_INTID_MASK&#160;&#160;&#160;0x000003FFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt ID. </p>

</div>
</div>
<a class="anchor" id="gaa65c329712b1a7f3ab12b0bf4ada058d"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_EOI_OFFSET&#160;&#160;&#160;0x00000010U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>End of Interrupt Reg. </p>

<p>Referenced by <a class="el" href="xscugic__low__level__example_8c.html#aa19b6eafe395a9ce4b9459234b832279">LowInterruptHandler()</a>, <a class="el" href="group__scugic__api.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler()</a>, and <a class="el" href="group__scugic__api.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>.</p>

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<a class="anchor" id="ga9f2c28f54da589ba1000235cfb0929ba"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_H</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; prevent circular inclusions </p>
<p>by using protection macros </p>

</div>
</div>
<a class="anchor" id="gaa8f4426fddda8466c267b661457dd54e"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSCUGIC_HI_PEND_OFFSET&#160;&#160;&#160;0x00000018U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Highest Pending Interrupt Register. </p>

</div>
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<a class="anchor" id="gac1bc762eba383937d08c41704737091c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_HW_H</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; prevent circular inclusions </p>
<p>by using protection macros </p>

</div>
</div>
<a class="anchor" id="ga80f182c20ecfcc115bca1ac7aae08889"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_IC_TYPE_OFFSET&#160;&#160;&#160;0x00000004U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Controller Type Register. </p>

</div>
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<a class="anchor" id="gab972b346f99c89c1913e6e49edc6fb0d"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSCUGIC_IMPL_MASK&#160;&#160;&#160;0x00000FFFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Implementor. </p>

</div>
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<a class="anchor" id="ga5f1418c8f0e05b7f928c2fff42b4514d"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSCUGIC_INT_ACK_OFFSET&#160;&#160;&#160;0x0000000CU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt ACK Reg. </p>

<p>Referenced by <a class="el" href="xscugic__low__level__example_8c.html#aa19b6eafe395a9ce4b9459234b832279">LowInterruptHandler()</a>, <a class="el" href="group__scugic__api.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler()</a>, and <a class="el" href="group__scugic__api.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ga2be546274013a123da9a0a8f21acfbc5"></a>
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<div class="memproto">
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          <td class="memname">#define XSCUGIC_INT_CFG_MASK&#160;&#160;&#160;0x00000003U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt configuration Mask. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType()</a>, <a class="el" href="group__scugic__api.html#ga19437ca93adc808161232c5667d7ca62">XScuGic_GetPriTrigTypeByDistAddr()</a>, <a class="el" href="group__scugic__api.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, and <a class="el" href="group__scugic__api.html#gac8e95bba26e2b07a882cb03750540b4d">XScuGic_SetPriTrigTypeByDistAddr()</a>.</p>

</div>
</div>
<a class="anchor" id="ga8c3e4a0e11aeeb05a7425826893a48b5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_INT_CFG_OFFSET&#160;&#160;&#160;0x00000C00U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Configuration Register 0xC00-0xCFC. </p>

</div>
</div>
<a class="anchor" id="ga53b866f6da52f01e4e230217b92203e1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_INT_CLR_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Each bit corresponds to an INT_ID. </p>

</div>
</div>
<a class="anchor" id="ga235b4d8d83653aae756d0377f6d42793"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_INT_EN_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Each bit corresponds to an INT_ID. </p>

</div>
</div>
<a class="anchor" id="gadd615bcd7723580422f99170f7beff31"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_INT_NS_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Each bit corresponds to an INT_ID. </p>

</div>
</div>
<a class="anchor" id="ga314e70261cb0c4c4da8019ff78c7e6f8"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_INTR_PRIO_MASK&#160;&#160;&#160;0x000000F8U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The Interrupt priority mask value. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, and <a class="el" href="group__scugic__api.html#gac8e95bba26e2b07a882cb03750540b4d">XScuGic_SetPriTrigTypeByDistAddr()</a>.</p>

</div>
</div>
<a class="anchor" id="ga63c9b51176e1db04adbbfa91b517d9a1"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_LSPI_MASK&#160;&#160;&#160;0x0000F800U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Number of Lockable Shared Peripheral Interrupts. </p>

</div>
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<a class="anchor" id="gaecd562b440bde835a8eee0c8a0e78249"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_MAX_INTR_PRIO_VAL&#160;&#160;&#160;248U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The maximum priority value that can be used in the GIC. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, and <a class="el" href="group__scugic__api.html#gac8e95bba26e2b07a882cb03750540b4d">XScuGic_SetPriTrigTypeByDistAddr()</a>.</p>

</div>
</div>
<a class="anchor" id="ga1027fc01e0c0efc80eadd0e6bb69f801"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_MAX_NUM_INTR_INPUTS&#160;&#160;&#160;195U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Maximum number of interrupt defined by Zynq Ultrascale Mp. </p>

<p>Referenced by <a class="el" href="xscugic__low__level__example_8c.html#aa19b6eafe395a9ce4b9459234b832279">LowInterruptHandler()</a>, <a class="el" href="group__scugic__api.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">XScuGic_CfgInitialize()</a>, <a class="el" href="group__scugic__api.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>, <a class="el" href="group__scugic__api.html#ga6146a0489a1c748ceeaee729639d48a7">XScuGic_Stop()</a>, <a class="el" href="group__scugic__api.html#ga66b2416be64a5e582e530ed9ed7f962c">XScuGic_UnmapAllInterruptsFromCpu()</a>, and <a class="el" href="group__scugic__api.html#gac7192c00a59e0cca27ed4c46f2755bb0">XScuGic_UnmapAllInterruptsFromCpuByDistAddr()</a>.</p>

</div>
</div>
<a class="anchor" id="ga5e47c517a580a243cde47a69d1fe6d50"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_NUM_INT_MASK&#160;&#160;&#160;0x0000001FU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Number of Interrupt IDs. </p>

</div>
</div>
<a class="anchor" id="gaeb56c44f88d7770aadf2b1fdbd3c24da"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PCELL_ID&#160;&#160;&#160;0xB105F00DU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PCELL ID value. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga081a9a62546b413d94e609894282a575">XScuGic_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="ga41becddbff3dcc589f4c9d70d0177ff6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PCELLID_OFFSET&#160;&#160;&#160;0x00000FF0U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Pcell ID Register. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga081a9a62546b413d94e609894282a575">XScuGic_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="gac000c78a5731608de6ea4951fff8b7a5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PEND_CLR_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Each bit corresponds to an INT_ID. </p>

</div>
</div>
<a class="anchor" id="ga1aea23f3bd1941b93443e441bd1e8e58"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PEND_INTID_MASK&#160;&#160;&#160;0x000003FFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Pending Interrupt ID. </p>

</div>
</div>
<a class="anchor" id="gaf9f9e786eda7eaa92e2a2661b6ff194c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PEND_SET_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Each bit corresponds to an INT_ID. </p>

</div>
</div>
<a class="anchor" id="ga3bd893d8bffa293ebf525ff6fc580f82"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PENDING_CLR_OFFSET&#160;&#160;&#160;0x00000280U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Pending Clear Register. </p>

</div>
</div>
<a class="anchor" id="gadf9985097ea7d040ad1eb0d1c45ade3f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PENDING_SET_OFFSET&#160;&#160;&#160;0x00000200U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Pending Set Register. </p>

</div>
</div>
<a class="anchor" id="gaa933fc8e5812dcef2571db933c761d10"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PERPHID_OFFSET&#160;&#160;&#160;0x00000FD0U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Peripheral ID Reg. </p>

</div>
</div>
<a class="anchor" id="gab0d1549e1fdc4ee0efda5b9a7d19f1c9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C00_MASK&#160;&#160;&#160;0x00000001U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gaa6af05ff49c40b1f95ddef70720c661d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C01_MASK&#160;&#160;&#160;0x00000002U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga841e2da3b34252affcbe1ae420dee5cd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C02_MASK&#160;&#160;&#160;0x00000004U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga1227f27b3f3566c377741ed4500864eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C03_MASK&#160;&#160;&#160;0x00000008U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gafb35a04b39200dc2531978c5b819a05f"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_PPI_C04_MASK&#160;&#160;&#160;0x00000010U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gaddc4c3db586fa77620204fc196c79196"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C05_MASK&#160;&#160;&#160;0x00000020U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gab4746833af92bb2cd60f47c5aef3c412"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C06_MASK&#160;&#160;&#160;0x00000040U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gac9103c688cb9f66402d43acdce1ec2d4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C07_MASK&#160;&#160;&#160;0x00000080U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga98cf40b1bb6de7edfe1034883780eb51"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C08_MASK&#160;&#160;&#160;0x00000100U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga5a79ff73cc31e2233f58a682a9421c5d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C09_MASK&#160;&#160;&#160;0x00000200U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga7a0c40850819f2d48d9ccaa274cd4881"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C10_MASK&#160;&#160;&#160;0x00000400U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga8318aad85340f5318de41b98da04100c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C11_MASK&#160;&#160;&#160;0x00000800U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gabd6aceee4c3c462bc1a9f95495d17181"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C12_MASK&#160;&#160;&#160;0x00001000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="gacc7fa22af93b8377b1f757d83a1a47a4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C13_MASK&#160;&#160;&#160;0x00002000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga6797b4c956ee74df8c35314ce817cc32"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C14_MASK&#160;&#160;&#160;0x00004000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga7fb6f58522fbce60a5d8e51ade739208"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_C15_MASK&#160;&#160;&#160;0x00008000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status. </p>

</div>
</div>
<a class="anchor" id="ga5b0239e9c600cc249f62309ca6ea7904"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PPI_STAT_OFFSET&#160;&#160;&#160;0x00000D00U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PPI Status Register. </p>

</div>
</div>
<a class="anchor" id="gaf56426a8af8b676cb9184cf2196b6bf4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PRIORITY_MASK&#160;&#160;&#160;0x000000FFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Each Byte corresponds to an INT_ID. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType()</a>, <a class="el" href="group__scugic__api.html#ga19437ca93adc808161232c5667d7ca62">XScuGic_GetPriTrigTypeByDistAddr()</a>, <a class="el" href="group__scugic__api.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, and <a class="el" href="group__scugic__api.html#gac8e95bba26e2b07a882cb03750540b4d">XScuGic_SetPriTrigTypeByDistAddr()</a>.</p>

</div>
</div>
<a class="anchor" id="ga5c2deb04ec9dad4c61b564f53b246ec0"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSCUGIC_PRIORITY_MAX&#160;&#160;&#160;0x000000FFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Highest value of a priority actually the lowest priority. </p>

</div>
</div>
<a class="anchor" id="ga4e103b71357ac53c890d8aebd3b80997"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_PRIORITY_OFFSET&#160;&#160;&#160;0x00000400U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Priority Level Register. </p>

</div>
</div>
<a class="anchor" id="ga0e4e42f499ef03373095daf342ffa988"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_REV_MASK&#160;&#160;&#160;0x00FFF000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Revision Number. </p>

</div>
</div>
<a class="anchor" id="ga9032b8ad311f376fd5d8fc046e4032f4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_RUN_PRIOR_OFFSET&#160;&#160;&#160;0x00000014U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Running Priority Reg. </p>

</div>
</div>
<a class="anchor" id="ga8ac1ba33bfaefe69aacd6221b0375f1c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_RUN_PRIORITY_MASK&#160;&#160;&#160;0x000000FFU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Priority. </p>

</div>
</div>
<a class="anchor" id="gaf8413fc164b51c233c05c6e48fdc0bf5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_SECURITY_OFFSET&#160;&#160;&#160;0x00000080U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Security Register. </p>

</div>
</div>
<a class="anchor" id="gab68476cc3813858c0c809ebfb4e28c74"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_SFI_TRIG_CPU_MASK&#160;&#160;&#160;0x00FF0000U</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>CPU Target list. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaca28a576540ab5fcd75cee1f38917ae4">XScuGic_SoftwareIntr()</a>.</p>

</div>
</div>
<a class="anchor" id="ga7956d8a2796ad6f92fafc49d92aa1a7d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSCUGIC_SFI_TRIG_INTID_MASK&#160;&#160;&#160;0x0000000FU</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Set to the INTID signaled to the CPU. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaca28a576540ab5fcd75cee1f38917ae4">XScuGic_SoftwareIntr()</a>.</p>

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          <td class="memname">#define XSCUGIC_SFI_TRIG_OFFSET&#160;&#160;&#160;0x00000F00U</td>
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<p>Software Triggered Interrupt Register. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaca28a576540ab5fcd75cee1f38917ae4">XScuGic_SoftwareIntr()</a>.</p>

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<p>0= Use a secure interrupt </p>

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<p>Target List filter b00-Use the target List b01-All CPUs except requester b10-To Requester b11-reserved. </p>

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          <td class="memname">#define XSCUGIC_SPI_CPU0_MASK&#160;&#160;&#160;0x00000001U</td>
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<p>CPU 0 Mask. </p>

<p>Referenced by <a class="el" href="xscugic__example_8c.html#a60ae419afb4e026a75cda3350d50f1cb">ScuGicExample()</a>.</p>

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          <td class="memname">#define XSCUGIC_SPI_CPU1_MASK&#160;&#160;&#160;0x00000002U</td>
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<p>CPU 1 Mask. </p>

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<p>CPU 2 Mask. </p>

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<p>CPU 3 Mask. </p>

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<p>CPU 4 Mask. </p>

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<p>CPU 5 Mask. </p>

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<p>CPU 6 Mask. </p>

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<p>CPU 7 Mask. </p>

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          <td class="memname">#define XSCUGIC_SPI_INT_ID_START&#160;&#160;&#160;0x20U</td>
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<p>First Interrupt Id for SPI interrupts. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaafd153e16238a1189c513846675e096a">XScuGic_Disable()</a>, <a class="el" href="group__scugic__api.html#ga0d183d23d05aac5d61cd640c5b39b275">XScuGic_DisableIntr()</a>, <a class="el" href="group__scugic__api.html#gac965b9e3ae7668a92cf07a65bde142cc">XScuGic_Enable()</a>, <a class="el" href="group__scugic__api.html#gadaa95193630e661a6a578f35a5e3ea1a">XScuGic_EnableIntr()</a>, <a class="el" href="group__scugic__api.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType()</a>, <a class="el" href="group__scugic__api.html#ga19437ca93adc808161232c5667d7ca62">XScuGic_GetPriTrigTypeByDistAddr()</a>, <a class="el" href="group__scugic__api.html#gaadf6b084a0540093dd64b8a8e3e74d6c">XScuGic_InterruptMapFromCpuByDistAddr()</a>, <a class="el" href="group__scugic__api.html#ga2a94f1a519d965f051d598e5a6b5a855">XScuGic_InterruptMaptoCpu()</a>, <a class="el" href="group__scugic__api.html#ga04f8ea74458251784b293e4ad98f2d74">XScuGic_InterruptUnmapFromCpu()</a>, <a class="el" href="group__scugic__api.html#ga51ba67d5953cb6b68a8d327b5e3103d7">XScuGic_InterruptUnmapFromCpuByDistAddr()</a>, <a class="el" href="group__scugic__api.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, and <a class="el" href="group__scugic__api.html#gac8e95bba26e2b07a882cb03750540b4d">XScuGic_SetPriTrigTypeByDistAddr()</a>.</p>

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<p>Each bit corresponds to an SPI input. </p>

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<p>SPI Status Register 0xd04-0xd7C. </p>

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<p>SPI Target Register 0x800-0x8FB. </p>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">s32 XScuGic_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> *&#160;</td>
          <td class="paramname"><em>ConfigPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>CfgInitialize a specific interrupt controller instance/driver. </p>
<p>The initialization entails:</p>
<ul>
<li>Initialize fields of the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> structure</li>
<li>Initial vector table with stub function calls</li>
<li>All interrupt sources are disabled</li>
</ul>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance. </td></tr>
    <tr><td class="paramname">ConfigPtr</td><td>Pointer to a config table for the particular device this driver is associated with. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>Device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use Config-&gt;BaseAddress for this parameters, passing the physical address instead.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if initialization was successful </li>
</ul>
</dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga231f58b4755a1856bbe3120370e5889e">XScuGic::Config</a>, <a class="el" href="group__scugic__api.html#ga699bf6b8bb8bfbb652b647b78cfae695">XScuGic_Config::DistBaseAddress</a>, <a class="el" href="group__scugic__api.html#ga7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a>, <a class="el" href="group__scugic__api.html#ga797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__api.html#ga1027fc01e0c0efc80eadd0e6bb69f801">XSCUGIC_MAX_NUM_INTR_INPUTS</a>, and <a class="el" href="group__scugic__api.html#ga6146a0489a1c748ceeaee729639d48a7">XScuGic_Stop()</a>.</p>

<p>Referenced by <a class="el" href="xscugic__example_8c.html#a60ae419afb4e026a75cda3350d50f1cb">ScuGicExample()</a>, <a class="el" href="xscugic__tapp__example_8c.html#aa8d3de2d2f90a1652a73b9a013be67c1">ScuGicInterruptSetup()</a>, and <a class="el" href="xscugic__tapp__example_8c.html#acb54aeda1ceadab17fcaf857c8bb083e">ScuGicSelfTestExample()</a>.</p>

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          <td class="memname">s32 XScuGic_Connect </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">Xil_InterruptHandler&#160;</td>
          <td class="paramname"><em>Handler</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallBackRef</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>Makes the connection between the Int_Id of the interrupt source and the associated handler that is to run when the interrupt is recognized. </p>
<p>The argument provided in this call as the Callbackref is used as the argument for the handler when it is called.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 </td></tr>
    <tr><td class="paramname">Handler</td><td>Handler for interrupt. </td></tr>
    <tr><td class="paramname">CallBackRef</td><td>Instance pointer of the connecting driver.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><pre class="fragment">    - XST_SUCCESS if the handler was connected correctly.
</pre></dd></dl>
<p>WARNING: The handler provided as an argument will overwrite any handler that was previously connected. </p>

<p>References <a class="el" href="group__scugic__api.html#ga231f58b4755a1856bbe3120370e5889e">XScuGic::Config</a>, <a class="el" href="group__scugic__api.html#ga7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a>, and <a class="el" href="group__scugic__api.html#ga797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>.</p>

<p>Referenced by <a class="el" href="xscugic__example_8c.html#a60ae419afb4e026a75cda3350d50f1cb">ScuGicExample()</a>.</p>

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          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
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<p>Initializes the GIC based on the device ID. </p>
<p>The initialization entails:</p>
<ul>
<li>Initialize distributor interface</li>
<li>Initialize cpu interface</li>
</ul>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>Device id to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<ul>
<li>XST_SUCCESS if initialization was successful </li>
</ul>

<p>References <a class="el" href="group__scugic__api.html#ga3de9d984ad4026ce214e09bf796cdc49">XScuGic_ConfigTable</a>.</p>

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<p>This function is the primary interrupt handler for the driver. </p>
<p>It must be connected to the interrupt source such that it is called when an interrupt of the interrupt controller is active. It will resolve which interrupts are active and enabled and call the appropriate interrupt handler. It uses the Interrupt Type information to determine when to acknowledge the interrupt. Highest priority interrupts are serviced first.</p>
<p>This function assumes that an interrupt vector table has been previously initialized. It does not verify that entries in the table are valid before calling an interrupt handler.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>Unique identifier for the ScuGic device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#gad9945cea79930d883f977fc97e1aa292">XSCUGIC_ACK_INTID_MASK</a>, <a class="el" href="group__scugic__api.html#ga3de9d984ad4026ce214e09bf796cdc49">XScuGic_ConfigTable</a>, <a class="el" href="group__scugic__api.html#gaa65c329712b1a7f3ab12b0bf4ada058d">XSCUGIC_EOI_OFFSET</a>, <a class="el" href="group__scugic__api.html#ga5f1418c8f0e05b7f928c2fff42b4514d">XSCUGIC_INT_ACK_OFFSET</a>, <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>, and <a class="el" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>.</p>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
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          <td>)</td>
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<p>Disables the interrupt source provided as the argument Int_Id such that the interrupt controller will not cause interrupts for the specified Int_Id. </p>
<p>The interrupt controller will continue to hold an interrupt condition for the Int_Id, but will not cause an interrupt. This API also unmaps the interrupt for the requesting CPU.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>Contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__api.html#ga7a61a9bf8e0b229925a5ddbf763b414b">XSCUGIC_DISABLE_OFFSET</a>, <a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, <a class="el" href="group__scugic__api.html#ga04f8ea74458251784b293e4ad98f2d74">XScuGic_InterruptUnmapFromCpu()</a>, and <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>.</p>

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          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>DistBaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Disables the interrupt source provided as the argument Int_Id so that the interrupt controller will not cause interrupts for the specified Int_Id. </p>
<p>The interrupt controller will continue to hold an interrupt condition for the Int_Id, but will not cause an interrupt.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Int_Id</td><td>Contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga7a61a9bf8e0b229925a5ddbf763b414b">XSCUGIC_DISABLE_OFFSET</a>, <a class="el" href="group__scugic__api.html#ga6c30ba79ea9505dc29b9cac4deea3df8">XScuGic_GetCpuID()</a>, <a class="el" href="group__scugic__api.html#ga51ba67d5953cb6b68a8d327b5e3103d7">XScuGic_InterruptUnmapFromCpuByDistAddr()</a>, <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>, <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>, and <a class="el" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>.</p>

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          <td class="memname">void XScuGic_Disconnect </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Updates the interrupt table with the Null Handler and NULL arguments at the location pointed at by the Int_Id. </p>
<p>This effectively disconnects that interrupt source from any handler. The interrupt is disabled also.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance to be worked on. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>Contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga231f58b4755a1856bbe3120370e5889e">XScuGic::Config</a>, <a class="el" href="group__scugic__api.html#ga7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a>, <a class="el" href="group__scugic__api.html#ga797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__api.html#ga7a61a9bf8e0b229925a5ddbf763b414b">XSCUGIC_DISABLE_OFFSET</a>, and <a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>.</p>

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          <td class="memname">void XScuGic_Enable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>Enables the interrupt source provided as the argument Int_Id. </p>
<p>Any pending interrupt condition for the specified Int_Id will occur after this function is called. This API also maps the interrupt to the requesting CPU.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>Contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, <a class="el" href="group__scugic__api.html#ga7e39be0cb9e08f4c9231f76e685a76cc">XSCUGIC_ENABLE_SET_OFFSET</a>, <a class="el" href="group__scugic__api.html#ga2a94f1a519d965f051d598e5a6b5a855">XScuGic_InterruptMaptoCpu()</a>, and <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>.</p>

<p>Referenced by <a class="el" href="xscugic__example_8c.html#a60ae419afb4e026a75cda3350d50f1cb">ScuGicExample()</a>.</p>

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          <td class="memname">void XScuGic_EnableIntr </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>DistBaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Enables the interrupt source provided as the argument Int_Id. </p>
<p>Any pending interrupt condition for the specified Int_Id will occur after this function is called.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Int_Id</td><td>Contains the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga7e39be0cb9e08f4c9231f76e685a76cc">XSCUGIC_ENABLE_SET_OFFSET</a>, <a class="el" href="group__scugic__api.html#ga6c30ba79ea9505dc29b9cac4deea3df8">XScuGic_GetCpuID()</a>, <a class="el" href="group__scugic__api.html#gaadf6b084a0540093dd64b8a8e3e74d6c">XScuGic_InterruptMapFromCpuByDistAddr()</a>, <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>, <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>, and <a class="el" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>.</p>

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          <td class="memname">u32 XScuGic_GetCpuID </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
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<p>Returns the CpuId variable. </p>
<dl class="section return"><dt>Returns</dt><dd>The CPU core number. </dd></dl>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga0d183d23d05aac5d61cd640c5b39b275">XScuGic_DisableIntr()</a>, and <a class="el" href="group__scugic__api.html#gadaa95193630e661a6a578f35a5e3ea1a">XScuGic_EnableIntr()</a>.</p>

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          <td class="memname">void XScuGic_GetPriorityTriggerType </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Priority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Trigger</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Gets the interrupt priority and trigger type for the specificd IRQ source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>IRQ source number to modify. </td></tr>
    <tr><td class="paramname">Priority</td><td>Pointer to the value of the priority of the IRQ source. This is a return value. </td></tr>
    <tr><td class="paramname">Trigger</td><td>Pointer to the value of the trigger of the IRQ source.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Pointer to the value of the trigger of the IRQ source. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__api.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>, <a class="el" href="group__scugic__api.html#ga2be546274013a123da9a0a8f21acfbc5">XSCUGIC_INT_CFG_MASK</a>, <a class="el" href="xscugic__hw_8h.html#a3921ef6af4f5fd6a35cb5089ef85a22a">XSCUGIC_INT_CFG_OFFSET_CALC</a>, <a class="el" href="group__scugic__api.html#gaf56426a8af8b676cb9184cf2196b6bf4">XSCUGIC_PRIORITY_MASK</a>, <a class="el" href="xscugic__hw_8h.html#af5f397349cab91733882c9d388498d5b">XSCUGIC_PRIORITY_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#a53759eec986eab489c00e26a566d2b00">XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#a93135e195fabc65c81e26163c8aabcdb">XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC</a>, and <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>.</p>

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          <td class="memname">void XScuGic_GetPriTrigTypeByDistAddr </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>DistBaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Priority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Trigger</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Gets the interrupt priority and trigger type for the specificd IRQ source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DistBaseAddress</td><td>Distributor base address </td></tr>
    <tr><td class="paramname">Int_Id</td><td>IRQ source number to modify </td></tr>
    <tr><td class="paramname">Priority</td><td>Pointer to the value of the priority of the IRQ source. This is a return value. </td></tr>
    <tr><td class="paramname">Trigger</td><td>Pointer to the value of the trigger of the IRQ source. This is a return value.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This API has the similar functionality of XScuGic_GetPriority TriggerType() and should be used when there is no InstancePtr. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga2be546274013a123da9a0a8f21acfbc5">XSCUGIC_INT_CFG_MASK</a>, <a class="el" href="xscugic__hw_8h.html#a3921ef6af4f5fd6a35cb5089ef85a22a">XSCUGIC_INT_CFG_OFFSET_CALC</a>, <a class="el" href="group__scugic__api.html#gaf56426a8af8b676cb9184cf2196b6bf4">XSCUGIC_PRIORITY_MASK</a>, <a class="el" href="xscugic__hw_8h.html#af5f397349cab91733882c9d388498d5b">XSCUGIC_PRIORITY_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#a53759eec986eab489c00e26a566d2b00">XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#a93135e195fabc65c81e26163c8aabcdb">XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>, and <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>.</p>

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          <td class="memname">void XScuGic_InterruptHandler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function is the primary interrupt handler for the driver. </p>
<p>It must be connected to the interrupt source such that it is called when an interrupt of the interrupt controller is active. It will resolve which interrupts are active and enabled and call the appropriate interrupt handler. It uses the Interrupt Type information to determine when to acknowledge the interrupt. Highest priority interrupts are serviced first.</p>
<p>This function assumes that an interrupt vector table has been previously initialized. It does not verify that entries in the table are valid before calling an interrupt handler.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga231f58b4755a1856bbe3120370e5889e">XScuGic::Config</a>, <a class="el" href="group__scugic__api.html#ga7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a>, <a class="el" href="group__scugic__api.html#gad9945cea79930d883f977fc97e1aa292">XSCUGIC_ACK_INTID_MASK</a>, <a class="el" href="group__scugic__api.html#ga2f3bba7c5247812158ef4fde7a0e7dfe">XScuGic_CPUReadReg</a>, <a class="el" href="group__scugic__api.html#ga2a4ba236ff7bfeab20b5ca81082f2b13">XScuGic_CPUWriteReg</a>, <a class="el" href="group__scugic__api.html#gaa65c329712b1a7f3ab12b0bf4ada058d">XSCUGIC_EOI_OFFSET</a>, <a class="el" href="group__scugic__api.html#ga5f1418c8f0e05b7f928c2fff42b4514d">XSCUGIC_INT_ACK_OFFSET</a>, and <a class="el" href="group__scugic__api.html#ga1027fc01e0c0efc80eadd0e6bb69f801">XSCUGIC_MAX_NUM_INTR_INPUTS</a>.</p>

<p>Referenced by <a class="el" href="xscugic__tapp__example_8c.html#aa8d3de2d2f90a1652a73b9a013be67c1">ScuGicInterruptSetup()</a>, and <a class="el" href="xscugic__example_8c.html#a89589e10926b9add4601dac19679feda">SetUpInterruptSystem()</a>.</p>

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          <td class="memname">void XScuGic_InterruptMapFromCpuByDistAddr </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>DistBaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Cpu_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Sets the target CPU for the interrupt of a peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DistBaseAddress</td><td>Device base address </td></tr>
    <tr><td class="paramname">Cpu_Id</td><td>CPU number from which the interrupt has to be unmapped </td></tr>
    <tr><td class="paramname">Int_Id</td><td>IRQ source number to modify</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xscugic__hw_8h.html#a68ccffbaf26e88803874e3fd9592bc80">XSCUGIC_IROUTER_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>, <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>, <a class="el" href="xscugic__hw_8h.html#aa2cf2e3acd2e8cf537c415276efa3a97">XSCUGIC_SPI_TARGET_OFFSET_CALC</a>, and <a class="el" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gadaa95193630e661a6a578f35a5e3ea1a">XScuGic_EnableIntr()</a>.</p>

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          <td class="memname">void XScuGic_InterruptMaptoCpu </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Cpu_Identifier</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Sets the target CPU for the interrupt of a peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">Cpu_Identifier</td><td>CPU number for which the interrupt has to be targeted For VERSAL_NET APU: 0 t0 3 bits sepcifies core id and 4 to 7 bits specifies cluster id of the targeted core. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>IRQ source number to modify.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>, <a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, <a class="el" href="xscugic__hw_8h.html#a68ccffbaf26e88803874e3fd9592bc80">XSCUGIC_IROUTER_OFFSET_CALC</a>, <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>, and <a class="el" href="xscugic__hw_8h.html#aa2cf2e3acd2e8cf537c415276efa3a97">XSCUGIC_SPI_TARGET_OFFSET_CALC</a>.</p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gac965b9e3ae7668a92cf07a65bde142cc">XScuGic_Enable()</a>.</p>

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          <td class="memname">void XScuGic_InterruptUnmapFromCpu </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Cpu_Identifier</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Unmaps specific SPI interrupt from the target CPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">Cpu_Identifier</td><td>CPU number from which the interrupt has to be unmapped. For VERSAL_NET APU: 0 t0 3 bits sepcifies core id and 4 to 7 bits specifies cluster id of the targeted core. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>IRQ source number to modify</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>, <a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>, and <a class="el" href="xscugic__hw_8h.html#aa2cf2e3acd2e8cf537c415276efa3a97">XSCUGIC_SPI_TARGET_OFFSET_CALC</a>.</p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaafd153e16238a1189c513846675e096a">XScuGic_Disable()</a>.</p>

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          <td class="memname">void XScuGic_InterruptUnmapFromCpuByDistAddr </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>DistBaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Cpu_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Unmaps specific SPI interrupt from the target CPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DistBaseAddress</td><td>Device base address </td></tr>
    <tr><td class="paramname">Cpu_Id</td><td>CPU number from which the interrupt has to be unmapped </td></tr>
    <tr><td class="paramname">Int_Id</td><td>IRQ source number to modify</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>

<p>References <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>, <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>, <a class="el" href="xscugic__hw_8h.html#aa2cf2e3acd2e8cf537c415276efa3a97">XSCUGIC_SPI_TARGET_OFFSET_CALC</a>, and <a class="el" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga0d183d23d05aac5d61cd640c5b39b275">XScuGic_DisableIntr()</a>.</p>

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          <td class="memname">u8 XScuGic_IsInitialized </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Checks whether the XScGic is initialized or not given the device ID. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>ID of the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns 1 if initialized otherwise 0. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga699bf6b8bb8bfbb652b647b78cfae695">XScuGic_Config::DistBaseAddress</a>, <a class="el" href="group__scugic__api.html#ga94cd5e2c3a1ab5b6c282d76bead5d616">XSCUGIC_DIST_EN_OFFSET</a>, <a class="el" href="group__scugic__api.html#gabd696b30c6257dea212cb9925ba73796">XSCUGIC_EN_INT_MASK</a>, <a class="el" href="group__scugic__api.html#gab2c0554b809121cc91a96fcd8c749c25">XScuGic_LookupConfig()</a>, and <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> * XScuGic_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Looks up the device configuration based on the unique device ID. </p>
<p>A table contains the configuration info for each device in the system.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>Unique identifier for a device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>A pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> configuration structure for the specified device, or NULL if the device is not found. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga3de9d984ad4026ce214e09bf796cdc49">XScuGic_ConfigTable</a>.</p>

<p>Referenced by <a class="el" href="xscugic__example_8c.html#a60ae419afb4e026a75cda3350d50f1cb">ScuGicExample()</a>, <a class="el" href="xscugic__tapp__example_8c.html#aa8d3de2d2f90a1652a73b9a013be67c1">ScuGicInterruptSetup()</a>, <a class="el" href="xscugic__tapp__example_8c.html#acb54aeda1ceadab17fcaf857c8bb083e">ScuGicSelfTestExample()</a>, and <a class="el" href="group__scugic__api.html#ga72b9aec992716861e5f0929e4d0d9f7c">XScuGic_IsInitialized()</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> * XScuGic_LookupConfigBaseAddr </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BaseAddress</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>Looks up the device configuration based on the BaseAddress. </p>
<p>The return value will refer to an entry in the device configuration table defined in the <a class="el" href="xscugic__g_8c.html">xscugic_g.c</a> file.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>Base address of the device.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>A pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> configuration structure for the specified device, or NULL if the device is not found. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga3de9d984ad4026ce214e09bf796cdc49">XScuGic_ConfigTable</a>.</p>

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          <td class="memname">void XScuGic_RegisterHandler </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>BaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">s32&#160;</td>
          <td class="paramname"><em>InterruptID</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">Xil_InterruptHandler&#160;</td>
          <td class="paramname"><em>IntrHandler</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallBackRef</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register a handler function for a specific interrupt ID. </p>
<p>The vector table of the interrupt controller is updated, overwriting any previous handler. The handler function will be called when an interrupt occurs for the given interrupt ID.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>CPU Interface Register base address of the interrupt controller whose vector table will be modified. </td></tr>
    <tr><td class="paramname">InterruptID</td><td>Interrupt ID to be associated with the input handler. </td></tr>
    <tr><td class="paramname">IntrHandler</td><td>Function pointer that will be added to the vector table for the given interrupt ID. </td></tr>
    <tr><td class="paramname">CallBackRef</td><td>Argument that will be passed to the new handler function when it is called. This is user-specific.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This function has no effect if the input base address is invalid. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga7ea39fc648dff09faa2a238e9a054089">XScuGic_Config::HandlerTable</a>.</p>

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          <td class="memname">s32 XScuGic_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Runs a self-test on the driver/device. </p>
<p>This test reads the ID registers and compares them.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><pre class="fragment">    -XST_SUCCESS if self-test is successful.
    -XST_FAILURE if the self-test is not successful.</pre> </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__api.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>, <a class="el" href="group__scugic__api.html#gaeb56c44f88d7770aadf2b1fdbd3c24da">XSCUGIC_PCELL_ID</a>, and <a class="el" href="group__scugic__api.html#ga41becddbff3dcc589f4c9d70d0177ff6">XSCUGIC_PCELLID_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="xscugic__example_8c.html#a60ae419afb4e026a75cda3350d50f1cb">ScuGicExample()</a>.</p>

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          <td class="memname">void XScuGic_SetCpuID </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>CpuCoreId</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Updates the CpuId global variable. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CpuCoreId</td><td>CPU core number.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

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          <td class="memname">void XScuGic_SetPriorityTriggerType </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Priority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Trigger</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Sets the interrupt priority and trigger type for the specificd IRQ source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>IRQ source number to modify. </td></tr>
    <tr><td class="paramname">Priority</td><td>New priority for the IRQ source. 0 is highest priority, 0xF8(248) is lowest. There are 32 priority levels supported with a step of 8. Hence the supported priorities are 0, 8, 16, 32, 40 ..., 248. </td></tr>
    <tr><td class="paramname">Trigger</td><td>New trigger type for the IRQ source. Each bit pair describes the configuration for an INT_ID. SFI Read Only b10 always PPI Read Only depending on how the PPIs are configured. b01 Active HIGH level sensitive b11 Rising edge sensitive SPI LSB is read only. b01 Active HIGH level sensitive b11 Rising edge sensitive/</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__api.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>, <a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, <a class="el" href="group__scugic__api.html#ga2be546274013a123da9a0a8f21acfbc5">XSCUGIC_INT_CFG_MASK</a>, <a class="el" href="xscugic__hw_8h.html#a3921ef6af4f5fd6a35cb5089ef85a22a">XSCUGIC_INT_CFG_OFFSET_CALC</a>, <a class="el" href="group__scugic__api.html#ga314e70261cb0c4c4da8019ff78c7e6f8">XSCUGIC_INTR_PRIO_MASK</a>, <a class="el" href="group__scugic__api.html#gaecd562b440bde835a8eee0c8a0e78249">XSCUGIC_MAX_INTR_PRIO_VAL</a>, <a class="el" href="group__scugic__api.html#gaf56426a8af8b676cb9184cf2196b6bf4">XSCUGIC_PRIORITY_MASK</a>, <a class="el" href="xscugic__hw_8h.html#af5f397349cab91733882c9d388498d5b">XSCUGIC_PRIORITY_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#a53759eec986eab489c00e26a566d2b00">XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#a93135e195fabc65c81e26163c8aabcdb">XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC</a>, and <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>.</p>

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          <td class="memname">void XScuGic_SetPriTrigTypeByDistAddr </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>DistBaseAddress</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Priority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Trigger</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Sets the interrupt priority and trigger type for the specificd IRQ source. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DistBaseAddress</td><td>Distributor base address </td></tr>
    <tr><td class="paramname">Int_Id</td><td>IRQ source number to modify </td></tr>
    <tr><td class="paramname">Priority</td><td>New priority for the IRQ source. 0 is highest priority, 0xF8(248) is lowest. There are 32 priority levels supported with a step of 8. Hence the supported priorities are 0, 8, 16, 32, 40 ..., 248. </td></tr>
    <tr><td class="paramname">Trigger</td><td>New trigger type for the IRQ source. Each bit pair describes the configuration for an INT_ID. SFI Read Only b10 always PPI Read Only depending on how the PPIs are configured. b01 Active HIGH level sensitive b11 Rising edge sensitive SPI LSB is read only. b01 Active HIGH level sensitive b11 Rising edge sensitive/</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This API has the similar functionality of XScuGic_SetPriority TriggerType() and should be used when there is no InstancePtr. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga2be546274013a123da9a0a8f21acfbc5">XSCUGIC_INT_CFG_MASK</a>, <a class="el" href="xscugic__hw_8h.html#a3921ef6af4f5fd6a35cb5089ef85a22a">XSCUGIC_INT_CFG_OFFSET_CALC</a>, <a class="el" href="group__scugic__api.html#ga314e70261cb0c4c4da8019ff78c7e6f8">XSCUGIC_INTR_PRIO_MASK</a>, <a class="el" href="group__scugic__api.html#gaecd562b440bde835a8eee0c8a0e78249">XSCUGIC_MAX_INTR_PRIO_VAL</a>, <a class="el" href="group__scugic__api.html#gaf56426a8af8b676cb9184cf2196b6bf4">XSCUGIC_PRIORITY_MASK</a>, <a class="el" href="xscugic__hw_8h.html#af5f397349cab91733882c9d388498d5b">XSCUGIC_PRIORITY_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#a53759eec986eab489c00e26a566d2b00">XSCUGIC_RDIST_INT_CONFIG_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#a93135e195fabc65c81e26163c8aabcdb">XSCUGIC_RDIST_INT_PRIORITY_OFFSET_CALC</a>, <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>, <a class="el" href="group__scugic__api.html#ga1706d457c89d8e76f1d120cc6fad418b">XSCUGIC_SPI_INT_ID_START</a>, and <a class="el" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>.</p>

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          <td class="memname">s32 XScuGic_SoftwareIntr </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Int_Id</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Cpu_Identifier</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>Allows software to simulate an interrupt in the interrupt controller. </p>
<p>This function will only be successful when the interrupt controller has been started in simulation mode. A simulated interrupt allows the interrupt controller to be tested without any device to drive an interrupt input signal into it.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> instance. </td></tr>
    <tr><td class="paramname">Int_Id</td><td>Software interrupt ID to simulate an interrupt. </td></tr>
    <tr><td class="paramname">Cpu_Identifier</td><td>List of CPUs to send the interrupt. For VERSAL_NET bits 0-7 specifies core ID to send the interrupt. bits 8-15 specifies the cluster id.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<p>XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be simulated </p>

<p>References <a class="el" href="group__scugic__api.html#ga797e50fb56fbc19bc35f73896decaf82">XScuGic::IsReady</a>, <a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, <a class="el" href="group__scugic__api.html#gab68476cc3813858c0c809ebfb4e28c74">XSCUGIC_SFI_TRIG_CPU_MASK</a>, <a class="el" href="group__scugic__api.html#ga7956d8a2796ad6f92fafc49d92aa1a7d">XSCUGIC_SFI_TRIG_INTID_MASK</a>, and <a class="el" href="group__scugic__api.html#ga5152b8067164fc0208df744dd20edea4">XSCUGIC_SFI_TRIG_OFFSET</a>.</p>

<p>Referenced by <a class="el" href="xscugic__example_8c.html#a60ae419afb4e026a75cda3350d50f1cb">ScuGicExample()</a>.</p>

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          <td>(</td>
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          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>Checks if the interrupt target register contains all interrupts to be targeted for current CPU. </p>
<p>If they are programmed to be forwarded to current cpu, this API disable all interrupts and disable GIC distributor. This API also removes current CPU from interrupt target registers for all interrupt.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the instance to be worked on.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga7a61a9bf8e0b229925a5ddbf763b414b">XSCUGIC_DISABLE_OFFSET</a>, <a class="el" href="group__scugic__api.html#ga94cd5e2c3a1ab5b6c282d76bead5d616">XSCUGIC_DIST_EN_OFFSET</a>, <a class="el" href="group__scugic__api.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>, <a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, <a class="el" href="xscugic__hw_8h.html#a37b4c6eb0a94fe5e17b6ce5ddc021f5b">XSCUGIC_EN_DIS_OFFSET_CALC</a>, <a class="el" href="group__scugic__api.html#gabd696b30c6257dea212cb9925ba73796">XSCUGIC_EN_INT_MASK</a>, <a class="el" href="xscugic__hw_8h.html#a68ccffbaf26e88803874e3fd9592bc80">XSCUGIC_IROUTER_OFFSET_CALC</a>, <a class="el" href="group__scugic__api.html#ga1027fc01e0c0efc80eadd0e6bb69f801">XSCUGIC_MAX_NUM_INTR_INPUTS</a>, and <a class="el" href="xscugic__hw_8h.html#aa2cf2e3acd2e8cf537c415276efa3a97">XSCUGIC_SPI_TARGET_OFFSET_CALC</a>.</p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">XScuGic_CfgInitialize()</a>.</p>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_scu_gic.html">XScuGic</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Cpu_Identifier</em>&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Unmaps all SPI interrupts from the target CPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>Pointer to the instance to be worked on. </td></tr>
    <tr><td class="paramname">Cpu_Identifier</td><td>CPU number from which the interrupts has to be unmapped.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga3d639fe1851f9d833367fb4322390eeb">XScuGic_DistReadReg</a>, <a class="el" href="group__scugic__api.html#ga22e9f81ed00f7cc39df1c6e76988fdb1">XScuGic_DistWriteReg</a>, <a class="el" href="group__scugic__api.html#ga1027fc01e0c0efc80eadd0e6bb69f801">XSCUGIC_MAX_NUM_INTR_INPUTS</a>, and <a class="el" href="xscugic__hw_8h.html#aa2cf2e3acd2e8cf537c415276efa3a97">XSCUGIC_SPI_TARGET_OFFSET_CALC</a>.</p>

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          <td class="memname">void XScuGic_UnmapAllInterruptsFromCpuByDistAddr </td>
          <td>(</td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>DistBaseAddress</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Cpu_Id</em>&#160;</td>
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          <td>)</td>
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<p>Unmaps all SPI interrupts from the target CPU. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DistBaseAddress</td><td>Device base address </td></tr>
    <tr><td class="paramname">Cpu_Id</td><td>CPU number from which the interrupts has to be unmapped</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="group__scugic__api.html#ga1027fc01e0c0efc80eadd0e6bb69f801">XSCUGIC_MAX_NUM_INTR_INPUTS</a>, <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>, <a class="el" href="xscugic__hw_8h.html#aa2cf2e3acd2e8cf537c415276efa3a97">XSCUGIC_SPI_TARGET_OFFSET_CALC</a>, and <a class="el" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>.</p>

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<h2 class="groupheader">Variable Documentation</h2>
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<p>CallBackRef is the callback reference passed in by the upper layer when setting the Interrupt handler for specific interrupt ID, and it will passed back to Interrupt handler when it is invoked. </p>

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<p>Configuration table entry. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">XScuGic_CfgInitialize()</a>, <a class="el" href="group__scugic__api.html#ga48f9dd531aa861a74e6bd627943573ea">XScuGic_Connect()</a>, <a class="el" href="group__scugic__api.html#gad162acedbbd41fd890fc7f2225ed480b">XScuGic_Disconnect()</a>, and <a class="el" href="group__scugic__api.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>.</p>

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<p>CPU Interface Register base address. </p>

<p>Referenced by <a class="el" href="xscugic__example_8c.html#a60ae419afb4e026a75cda3350d50f1cb">ScuGicExample()</a>, <a class="el" href="xscugic__tapp__example_8c.html#aa8d3de2d2f90a1652a73b9a013be67c1">ScuGicInterruptSetup()</a>, <a class="el" href="xscugic__tapp__example_8c.html#acb54aeda1ceadab17fcaf857c8bb083e">ScuGicSelfTestExample()</a>, and <a class="el" href="xscugic__low__level__example_8c.html#a41e86f1c34d18e351ce42a5aa0c4ce2e">SetupInterruptSystem()</a>.</p>

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          <td class="memname">u16 XScuGic_Config::DeviceId</td>
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<p>Unique ID of device. </p>

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<p>Distributor Register base address. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">XScuGic_CfgInitialize()</a>, and <a class="el" href="group__scugic__api.html#ga72b9aec992716861e5f0929e4d0d9f7c">XScuGic_IsInitialized()</a>.</p>

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<p>Interrupt Handler. </p>

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          <td class="memname">XScuGic_VectorTableEntry XScuGic_Config::HandlerTable[<a class="el" href="group__scugic__api.html#ga1027fc01e0c0efc80eadd0e6bb69f801">XSCUGIC_MAX_NUM_INTR_INPUTS</a>]</td>
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<p>Vector table of interrupt handlers. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">XScuGic_CfgInitialize()</a>, <a class="el" href="group__scugic__api.html#ga48f9dd531aa861a74e6bd627943573ea">XScuGic_Connect()</a>, <a class="el" href="group__scugic__api.html#gad162acedbbd41fd890fc7f2225ed480b">XScuGic_Disconnect()</a>, <a class="el" href="group__scugic__api.html#gaa26a952ecd376be0bc3d8433023d1364">XScuGic_InterruptHandler()</a>, and <a class="el" href="group__scugic__api.html#gac1d1444968ff82f78505eeae32a2e471">XScuGic_RegisterHandler()</a>.</p>

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<p>Device is initialized and ready. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#gaf8e0bfe31c0fa2ca654c36715a3c13f8">XScuGic_CfgInitialize()</a>, <a class="el" href="group__scugic__api.html#ga48f9dd531aa861a74e6bd627943573ea">XScuGic_Connect()</a>, <a class="el" href="group__scugic__api.html#gaafd153e16238a1189c513846675e096a">XScuGic_Disable()</a>, <a class="el" href="group__scugic__api.html#gad162acedbbd41fd890fc7f2225ed480b">XScuGic_Disconnect()</a>, <a class="el" href="group__scugic__api.html#gac965b9e3ae7668a92cf07a65bde142cc">XScuGic_Enable()</a>, <a class="el" href="group__scugic__api.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType()</a>, <a class="el" href="group__scugic__api.html#ga081a9a62546b413d94e609894282a575">XScuGic_SelfTest()</a>, <a class="el" href="group__scugic__api.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, and <a class="el" href="group__scugic__api.html#gaca28a576540ab5fcd75cee1f38917ae4">XScuGic_SoftwareIntr()</a>.</p>

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<p>Intc Statistics. </p>

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          <td class="memname"><a class="el" href="struct_x_scu_gic___config.html">XScuGic_Config</a> XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES]</td>
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<b>Initial value:</b><div class="fragment"><div class="line">= {</div>
<div class="line">        {</div>
<div class="line">                (u16)XPAR_SCUGIC_0_DEVICE_ID,  </div>
<div class="line">                (u32)XPAR_SCUGIC_0_CPU_BASEADDR,  </div>
<div class="line">                (u32)XPAR_SCUGIC_0_DIST_BASEADDR,  </div>
<div class="line">                {{0}}  </div>
<div class="line">        }</div>
<div class="line">}</div>
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<p>This table contains configuration information for each GIC device in the system. </p>
<p>Config table.</p>
<p>The <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ACK it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.</p>
<p>Refer to the <a class="el" href="struct_x_scu_gic___config.html" title="This typedef contains configuration information for the device. ">XScuGic_Config</a> data structure in <a class="el" href="xscugic_8h.html">xscugic.h</a> for details on how this table should be initialized. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga2cbf5d5ac5273e00c0b16bd33ad0707f">XScuGic_DeviceInitialize()</a>, <a class="el" href="group__scugic__api.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler()</a>, <a class="el" href="group__scugic__api.html#gab2c0554b809121cc91a96fcd8c749c25">XScuGic_LookupConfig()</a>, and <a class="el" href="group__scugic__api.html#ga805a47295123177a48b07fccfe037702">XScuGic_LookupConfigBaseAddr()</a>.</p>

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<p>Config table. </p>
<p>Config table.</p>
<p>The <a class="el" href="struct_x_scu_gic.html" title="The XScuGic driver instance data. ">XScuGic</a> driver must know when to acknowledge the interrupt. The entry which specifies this as a bit mask where each bit corresponds to a specific interrupt. A bit set indicates to ACK it before servicing it. Generally, acknowledge before service is used when the interrupt signal is edge-sensitive, and after when the signal is level-sensitive.</p>
<p>Refer to the <a class="el" href="struct_x_scu_gic___config.html" title="This typedef contains configuration information for the device. ">XScuGic_Config</a> data structure in <a class="el" href="xscugic_8h.html">xscugic.h</a> for details on how this table should be initialized. </p>

<p>Referenced by <a class="el" href="group__scugic__api.html#ga2cbf5d5ac5273e00c0b16bd33ad0707f">XScuGic_DeviceInitialize()</a>, <a class="el" href="group__scugic__api.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler()</a>, <a class="el" href="group__scugic__api.html#gab2c0554b809121cc91a96fcd8c749c25">XScuGic_LookupConfig()</a>, and <a class="el" href="group__scugic__api.html#ga805a47295123177a48b07fccfe037702">XScuGic_LookupConfigBaseAddr()</a>.</p>

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